Alternatives and similar repositories for f4pga-arch-defs

Users that are interested in f4pga-arch-defs are comparing it to the libraries listed below

• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆282Updated last year
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆417Updated last year
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆485Updated this week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆252Updated last year
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆370Updated 10 months ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆462Updated 3 weeks ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆319Updated last year
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆354Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆242Updated 4 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆315Updated 11 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆311Updated 2 weeks ago
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆223Updated last year
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆434Updated 4 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆161Updated 9 months ago
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆435Updated 3 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated 2 weeks ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆336Updated last year
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆283Updated last year
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆243Updated 7 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆288Updated 3 weeks ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆223Updated 2 months ago
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆299Updated 4 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆447Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆252Updated last year
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆436Updated 2 months ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆320Updated 2 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆737Updated 3 weeks ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆221Updated 3 weeks ago