FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
☆314Sep 25, 2026Updated this week
Alternatives and similar repositories for f4pga-arch-defs
Users that are interested in f4pga-arch-defs are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Example designs showing different ways to use F4PGA toolchains.☆289Mar 27, 2024Updated 2 years ago
- Documenting the Xilinx 7-series bit-stream format.☆918Jun 5, 2025Updated last year
- FOSS Flow For FPGA☆451Jan 6, 2025Updated last year
- FPGA tool performance profiling☆108Feb 24, 2024Updated 2 years ago
- nextpnr portable FPGA place and route tool☆1,760Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,273Updated this week
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 8 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Open-source FPGA research and prototyping framework.☆212Aug 8, 2024Updated 2 years ago
- Experimental flows using nextpnr for Xilinx devices☆268Oct 11, 2024Updated last year
- FPGA Assembly (FASM) Parser and Generator☆104Jul 25, 2022Updated 4 years ago
- Documenting the Lattice ECP5 bit-stream format.☆472Sep 20, 2026Updated last week
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆86Feb 9, 2022Updated 4 years ago
- VHDL synthesis (based on ghdl)☆370Sep 20, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An Open-source FPGA IP Generator☆1,157Updated this week
- Yosys Open SYnthesis Suite☆4,778Updated this week
- An abstraction library for interfacing EDA tools☆801Sep 15, 2026Updated 2 weeks ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated last year
- Documenting Lattice's 28nm FPGA parts☆154Jul 19, 2026Updated 2 months ago
- Python interface to FPGA interchange format☆41Oct 19, 2022Updated 3 years ago
- Multi-platform nightly builds of open source FPGA tools☆306Nov 3, 2021Updated 4 years ago
- Universal utility for programming FPGA☆1,746Sep 23, 2026Updated last week
- Build Customized FPGA Implementations for Vivado☆390Updated this week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Small footprint and configurable HyperBus core☆14Jul 6, 2022Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆99Sep 9, 2026Updated 3 weeks ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆553Sep 19, 2026Updated last week
- Build your hardware, easily!☆4,137Updated this week
- Project X-Ray Database: XC7 Series☆77Dec 14, 2021Updated 4 years ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Jan 30, 2025Updated last year
- A padring generator for ASICs☆26May 17, 2023Updated 3 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,466Updated this week
- A modern hardware definition language and toolchain based on Python☆2,095Sep 18, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- A Python toolbox for building complex digital hardware☆1,329Jan 5, 2026Updated 8 months ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,188Sep 21, 2026Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆102Aug 20, 2026Updated last month
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆231Jan 11, 2026Updated 8 months ago
- Copyleftist's Standard Cell Library☆105May 2, 2024Updated 2 years ago
- Place and route tool for FPGAs☆423Jul 28, 2019Updated 7 years ago