f4pga / f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
☆280Updated last week
Alternatives and similar repositories for f4pga-arch-defs:
Users that are interested in f4pga-arch-defs are comparing it to the libraries listed below
- Example designs showing different ways to use F4PGA toolchains.☆272Updated 11 months ago
- FOSS Flow For FPGA☆375Updated 2 months ago
- Small footprint and configurable DRAM core☆396Updated 2 months ago
- VeeR EL2 Core☆266Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆429Updated last week
- Experimental flows using nextpnr for Xilinx devices☆227Updated 5 months ago
- A huge VHDL library for FPGA development☆378Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆382Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆211Updated this week
- VHDL synthesis (based on ghdl)☆326Updated 3 weeks ago
- A simple RISC-V processor for use in FPGA designs.☆269Updated 6 months ago
- Multi-platform nightly builds of open source FPGA tools☆295Updated 3 years ago
- SystemVerilog to Verilog conversion☆600Updated 2 weeks ago
- FuseSoC standard core library☆127Updated last month
- A simple, basic, formally verified UART controller☆290Updated last year
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆573Updated 4 years ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆388Updated 3 weeks ago
- Bus bridges and other odds and ends☆523Updated last month
- FuseSoC-based SoC for VeeR EH1 and EL2☆308Updated 3 months ago
- An abstraction library for interfacing EDA tools☆668Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆153Updated 11 months ago
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆236Updated last week
- Common SystemVerilog components☆583Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆558Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆308Updated this week
- CORE-V Family of RISC-V Cores☆240Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆459Updated last month
- Fabric generator and CAD tools☆162Updated 2 weeks ago
- Build Customized FPGA Implementations for Vivado☆305Updated 2 weeks ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆418Updated 6 months ago