Alternatives and similar repositories for f4pga-arch-defs

Users that are interested in f4pga-arch-defs are comparing it to the libraries listed below

• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆394Updated 6 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆221Updated 2 weeks ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆244Updated 9 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆305Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆288Updated 2 weeks ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆144Updated last month
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆461Updated this week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆424Updated last week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆321Updated 7 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆190Updated this week
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆391Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆398Updated 2 weeks ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆333Updated 4 months ago
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆216Updated 8 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆572Updated 2 months ago
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆416Updated 2 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 3 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆201Updated 4 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆336Updated last month
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆277Updated 4 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆333Updated 2 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆277Updated 10 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆271Updated 4 years ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆255Updated last week
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆153Updated this week
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆277Updated 5 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆283Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆645Updated 2 weeks ago