Alternatives and similar repositories for f4pga-arch-defs

Users that are interested in f4pga-arch-defs are comparing it to the libraries listed below

• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆275Updated last year
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆386Updated 4 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆334Updated 3 weeks ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆382Updated this week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆234Updated 7 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆136Updated last month
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆684Updated last week
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆157Updated last month
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆411Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆453Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆390Updated 3 weeks ago
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆295Updated 3 years ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆318Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆621Updated last month
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆412Updated last week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆302Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆275Updated 2 weeks ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆178Updated this week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆316Updated 5 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆552Updated 3 weeks ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆273Updated 8 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆217Updated last month
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆405Updated 2 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆324Updated 2 months ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆397Updated 3 weeks ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆268Updated 4 years ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆238Updated last week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆265Updated 2 months ago
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆209Updated 6 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆179Updated 3 weeks ago