ghdl / ghdl-yosys-pluginView external linksLinks
VHDL synthesis (based on ghdl)
☆355Jan 11, 2026Updated last month
Alternatives and similar repositories for ghdl-yosys-plugin
Users that are interested in ghdl-yosys-plugin are comparing it to the libraries listed below
Sorting:
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated last year
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Feb 2, 2025Updated last year
- VHDL 2008/93/87 simulator☆2,752Updated this week
- nextpnr portable FPGA place and route tool☆1,604Feb 6, 2026Updated last week
- A VHDL frontend for Yosys☆104Feb 27, 2017Updated 8 years ago
- An abstraction library for interfacing EDA tools☆750Updated this week
- Language server based on ghdl☆102May 14, 2025Updated 9 months ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 2 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- Experimental flows using nextpnr for Xilinx devices☆253Oct 11, 2024Updated last year
- VHDL compiler and simulator☆774Updated this week
- Yosys Open SYnthesis Suite☆4,272Updated this week
- Building and deploying container images for open source electronic design automation (EDA)☆120Oct 3, 2024Updated last year
- Multi-platform nightly builds of open source FPGA tools☆301Nov 3, 2021Updated 4 years ago
- VHDL related news.☆27Updated this week
- Library of reusable VHDL components☆28Mar 7, 2024Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Updated this week
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆301Feb 5, 2026Updated last week
- Universal utility for programming FPGA☆1,540Feb 3, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,387Updated this week
- A tiny Open POWER ISA softcore written in VHDL 2008☆710Feb 4, 2026Updated last week
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Aug 20, 2022Updated 3 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 9 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- A JSON library implemented in VHDL.☆82Updated this week
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆423Jan 27, 2026Updated 2 weeks ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆813Updated this week
- VHDL library 4 FPGAs☆185Updated this week
- Documenting the Xilinx 7-series bit-stream format.☆849Jun 5, 2025Updated 8 months ago
- Example designs showing different ways to use F4PGA toolchains.☆283Mar 27, 2024Updated last year
- crap-o-scope scope implementation for icestick☆20Jun 1, 2018Updated 7 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Oct 24, 2023Updated 2 years ago
- A curated list of awesome resources for HDL design and verification☆169Feb 6, 2026Updated last week
- Streaming based VHDL parser.☆84Jul 15, 2024Updated last year
- HDL symbol generator☆202Feb 2, 2023Updated 3 years ago
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆600Jul 30, 2025Updated 6 months ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆904Feb 7, 2026Updated last week