gatecat / nextpnr-xilinx
Experimental flows using nextpnr for Xilinx devices
☆228Updated 5 months ago
Alternatives and similar repositories for nextpnr-xilinx:
Users that are interested in nextpnr-xilinx are comparing it to the libraries listed below
- Example designs showing different ways to use F4PGA toolchains.☆272Updated 11 months ago
- SystemVerilog synthesis tool☆180Updated this week
- Small footprint and configurable DRAM core☆396Updated 2 months ago
- FuseSoC standard core library☆127Updated last month
- Small footprint and configurable Ethernet core☆223Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆211Updated last week
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆280Updated last week
- Fabric generator and CAD tools☆162Updated 2 weeks ago
- USB3 PIPE interface for Xilinx 7-Series☆209Updated 2 years ago
- ☆77Updated last year
- VHDL library 4 FPGAs☆175Updated this week
- A utility for Composing FPGA designs from Peripherals☆171Updated 2 months ago
- Documenting the Lattice ECP5 bit-stream format.☆408Updated 2 months ago
- SoC based on VexRiscv and ICE40 UP5K☆153Updated 11 months ago
- Multi-platform nightly builds of open source FPGA tools☆295Updated 3 years ago
- Opensource DDR3 Controller☆276Updated this week
- A Video display simulator☆162Updated 7 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆382Updated last week
- ☆129Updated 3 months ago
- A simple, basic, formally verified UART controller☆290Updated last year
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆74Updated 3 years ago
- VHDL synthesis (based on ghdl)☆326Updated 3 weeks ago
- FOSS Flow For FPGA☆375Updated 2 months ago
- Bus bridges and other odds and ends☆523Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆143Updated 8 months ago
- Example LED blinking project for your FPGA dev board of choice☆171Updated 2 weeks ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆110Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- Naive Educational RISC V processor☆79Updated 5 months ago
- USB Serial on the TinyFPGA BX☆135Updated 3 years ago