Experimental flows using nextpnr for Xilinx devices
☆260Oct 11, 2024Updated last year
Alternatives and similar repositories for nextpnr-xilinx
Users that are interested in nextpnr-xilinx are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Documenting the Xilinx 7-series bit-stream format.☆895Jun 5, 2025Updated last year
- nextpnr portable FPGA place and route tool☆1,694Jun 5, 2026Updated last week
- Documenting Lattice's 28nm FPGA parts☆152Feb 26, 2026Updated 3 months ago
- Experimental flows using nextpnr for Xilinx devices☆65Jun 9, 2026Updated last week
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆82Feb 9, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Build Customized FPGA Implementations for Vivado☆381Updated this week
- Example designs showing different ways to use F4PGA toolchains.☆288Mar 27, 2024Updated 2 years ago
- VHDL synthesis (based on ghdl)☆366May 14, 2026Updated last month
- Universal utility for programming FPGA☆1,651Jun 4, 2026Updated last week
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102May 16, 2023Updated 3 years ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆17May 23, 2020Updated 6 years ago
- Yosys Open SYnthesis Suite☆4,531Updated this week
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆30Jul 10, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Cyclone V bitstream reverse-engineering project☆133Oct 19, 2023Updated 2 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,171Feb 26, 2026Updated 3 months ago
- System on Chip toolkit for Amaranth HDL☆101May 23, 2026Updated 3 weeks ago
- An abstraction library for interfacing EDA tools☆771Apr 24, 2026Updated last month
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆308Updated this week
- RFCs for changes to the Amaranth language and standard components☆18May 3, 2026Updated last month
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆111Mar 23, 2026Updated 2 months ago
- Documenting the Lattice ECP5 bit-stream format.☆460May 9, 2026Updated last month
- FOSS Flow For FPGA☆440Jan 6, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Miscellaneous ULX3S examples (advanced)☆85Feb 7, 2026Updated 4 months ago
- Project Apicula 🐝: bitstream documentation for Gowin FPGAs☆664Updated this week
- A modern hardware definition language and toolchain based on Python☆2,028May 25, 2026Updated 3 weeks ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 4 months ago
- Build your hardware, easily!☆3,927Updated this week
- 妖刀夢渡☆64Apr 2, 2019Updated 7 years ago
- Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more☆17Apr 3, 2025Updated last year
- SystemVerilog frontend for Yosys☆229Updated this week
- Ultimate ECP5 development board☆117Jul 4, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An Open-source FPGA IP Generator☆1,114Updated this week
- Basic Pong you can extend with rotary, sound, vga generator and autopilot☆11Oct 26, 2021Updated 4 years ago
- Running Rust on the (Linux) Litex VexRiscv FPGA SOC☆16Jun 3, 2025Updated last year
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,416Jun 5, 2026Updated last week
- [MIGRATED to https://codeberg.org/prjunnamed/prjcombine/] An FPGA reverse engineering and documentation project☆65Mar 12, 2026Updated 3 months ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,237Updated this week
- FPGA Assembly (FASM) Parser and Generator☆102Jul 25, 2022Updated 3 years ago