Experimental flows using nextpnr for Xilinx devices
☆254Oct 11, 2024Updated last year
Alternatives and similar repositories for nextpnr-xilinx
Users that are interested in nextpnr-xilinx are comparing it to the libraries listed below
Sorting:
- Documenting the Xilinx 7-series bit-stream format.☆851Jun 5, 2025Updated 9 months ago
- nextpnr portable FPGA place and route tool☆1,627Updated this week
- Documenting Lattice's 28nm FPGA parts☆149Feb 26, 2026Updated last week
- Experimental flows using nextpnr for Xilinx devices☆57Feb 26, 2026Updated last week
- Example designs showing different ways to use F4PGA toolchains.☆285Mar 27, 2024Updated last year
- Universal utility for programming FPGA☆1,554Feb 26, 2026Updated last week
- Build Customized FPGA Implementations for Vivado☆355Updated this week
- VHDL synthesis (based on ghdl)☆356Jan 11, 2026Updated last month
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆82Feb 9, 2022Updated 4 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102May 16, 2023Updated 2 years ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,132Feb 26, 2026Updated last week
- Cyclone V bitstream reverse-engineering project☆131Oct 19, 2023Updated 2 years ago
- An abstraction library for interfacing EDA tools☆756Feb 18, 2026Updated 2 weeks ago
- Yosys Open SYnthesis Suite☆4,305Updated this week
- Documenting the Lattice ECP5 bit-stream format.☆447Feb 26, 2026Updated last week
- System on Chip toolkit for Amaranth HDL☆100Feb 24, 2026Updated last week
- Project Apicula 🐝: bitstream documentation for Gowin FPGAs☆640Updated this week
- Miscellaneous ULX3S examples (advanced)☆83Feb 7, 2026Updated 3 weeks ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆302Feb 25, 2026Updated last week
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆29Jul 10, 2024Updated last year
- FOSS Flow For FPGA☆425Jan 6, 2025Updated last year
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆17May 23, 2020Updated 5 years ago
- 妖刀夢渡☆63Apr 2, 2019Updated 6 years ago
- Basic Pong you can extend with rotary, sound, vga generator and autopilot☆11Oct 26, 2021Updated 4 years ago
- A modern hardware definition language and toolchain based on Python☆1,914Updated this week
- RFCs for changes to the Amaranth language and standard components☆18Jan 26, 2026Updated last month
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆92Feb 24, 2026Updated last week
- Ultimate ECP5 development board☆116Jul 4, 2019Updated 6 years ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,210Updated this week
- VHDL library 4 FPGAs☆185Feb 23, 2026Updated last week
- ECP5 breakout board in a feather physical format☆523Nov 6, 2024Updated last year
- SystemVerilog frontend for Yosys☆202Feb 22, 2026Updated last week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆496Updated this week
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Feb 12, 2026Updated 3 weeks ago
- Build your hardware, easily!☆3,747Updated this week
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,398Jan 5, 2026Updated 2 months ago
- An Open-source FPGA IP Generator☆1,056Updated this week
- Small footprint and configurable DRAM core☆475Feb 19, 2026Updated 2 weeks ago