Alternatives and similar repositories for nextpnr-xilinx

Users that are interested in nextpnr-xilinx are comparing it to the libraries listed below

• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆223Updated 10 months ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆282Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆299Updated this week
• olofk / corescore
  CoreScore
  ☆171Updated last month
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆242Updated 4 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆186Updated last week
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated last week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆462Updated 3 weeks ago
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆272Updated this week
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆299Updated 4 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆184Updated this week
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated 2 months ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆118Updated 4 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆81Updated 3 years ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆417Updated last year
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆319Updated last year
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆189Updated 3 weeks ago
• ldoolitt / vhd2vl
  ☆137Updated last year
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆146Updated 2 years ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆186Updated last year
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆128Updated 7 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆354Updated last week
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• pieter3d / simview
  ☆88Updated 2 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆161Updated 9 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated 2 years ago