gatecat / nextpnr-xilinxLinks
Experimental flows using nextpnr for Xilinx devices
☆245Updated last year
Alternatives and similar repositories for nextpnr-xilinx
Users that are interested in nextpnr-xilinx are comparing it to the libraries listed below
Sorting:
- Example designs showing different ways to use F4PGA toolchains.☆276Updated last year
- SystemVerilog synthesis tool☆217Updated 8 months ago
- FuseSoC standard core library☆147Updated 5 months ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆295Updated this week
- A simple, basic, formally verified UART controller☆312Updated last year
- Small footprint and configurable DRAM core☆450Updated 3 weeks ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆237Updated 2 months ago
- FOSS Flow For FPGA☆412Updated 10 months ago
- SystemVerilog frontend for Yosys☆168Updated this week
- Example LED blinking project for your FPGA dev board of choice☆186Updated last month
- CoreScore☆167Updated 3 weeks ago
- User-friendly explanation of Yosys options☆112Updated 4 years ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago
- Fabric generator and CAD tools.☆206Updated this week
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆117Updated 4 years ago
- Multi-platform nightly builds of open source FPGA tools☆299Updated 4 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- Small footprint and configurable Ethernet core☆268Updated this week
- VHDL synthesis (based on ghdl)☆352Updated last week
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- ☆137Updated 11 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆183Updated last year
- Documenting the Lattice ECP5 bit-stream format.☆431Updated 2 weeks ago
- VHDL library 4 FPGAs☆181Updated last week
- Naive Educational RISC V processor☆91Updated last month
- USB3 PIPE interface for Xilinx 7-Series☆234Updated 3 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆425Updated 2 months ago
- Board definitions for Amaranth HDL☆121Updated 2 months ago
- ☆87Updated last month
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago