gatecat / nextpnr-xilinx
Experimental flows using nextpnr for Xilinx devices
☆234Updated 6 months ago
Alternatives and similar repositories for nextpnr-xilinx:
Users that are interested in nextpnr-xilinx are comparing it to the libraries listed below
- SystemVerilog synthesis tool☆190Updated last month
- FuseSoC standard core library☆134Updated last month
- Example designs showing different ways to use F4PGA toolchains.☆275Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆282Updated this week
- Small footprint and configurable DRAM core☆410Updated last week
- A utility for Composing FPGA designs from Peripherals☆178Updated 4 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆217Updated last month
- VHDL synthesis (based on ghdl)☆334Updated 2 weeks ago
- ☆78Updated last year
- CoreScore☆151Updated 3 months ago
- Small footprint and configurable Ethernet core☆236Updated 2 weeks ago
- SoC based on VexRiscv and ICE40 UP5K☆157Updated last month
- Naive Educational RISC V processor☆82Updated 6 months ago
- Example LED blinking project for your FPGA dev board of choice☆175Updated 2 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆76Updated 3 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆145Updated 10 months ago
- FOSS Flow For FPGA☆385Updated 4 months ago
- Fabric generator and CAD tools☆178Updated 2 weeks ago
- Documenting the Lattice ECP5 bit-stream format.☆411Updated this week
- SystemVerilog frontend for Yosys☆100Updated last week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- A simple, basic, formally verified UART controller☆299Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆138Updated 2 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆167Updated last year
- Multi-platform nightly builds of open source FPGA tools☆295Updated 3 years ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- Opensource DDR3 Controller☆319Updated 2 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆388Updated 2 weeks ago
- VHDL library 4 FPGAs☆177Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆453Updated 3 weeks ago