gatecat / nextpnr-xilinxLinks
Experimental flows using nextpnr for Xilinx devices
☆248Updated last year
Alternatives and similar repositories for nextpnr-xilinx
Users that are interested in nextpnr-xilinx are comparing it to the libraries listed below
Sorting:
- Example designs showing different ways to use F4PGA toolchains.☆281Updated last year
- SystemVerilog synthesis tool☆220Updated 9 months ago
- FuseSoC standard core library☆150Updated last week
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆298Updated this week
- Fabric generator and CAD tools.☆214Updated this week
- A simple, basic, formally verified UART controller☆318Updated last year
- CoreScore☆170Updated last month
- Example LED blinking project for your FPGA dev board of choice☆189Updated this week
- SystemVerilog frontend for Yosys☆181Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆160Updated 9 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- A utility for Composing FPGA designs from Peripherals☆185Updated 11 months ago
- VHDL synthesis (based on ghdl)☆353Updated last month
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Naive Educational RISC V processor☆92Updated 2 months ago
- FOSS Flow For FPGA☆415Updated 11 months ago
- ☆137Updated last year
- Small footprint and configurable DRAM core☆460Updated 3 weeks ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆81Updated 3 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆186Updated last year
- VHDL library 4 FPGAs☆182Updated this week
- Multi-platform nightly builds of open source FPGA tools☆299Updated 4 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆118Updated 4 years ago
- Small footprint and configurable Ethernet core☆271Updated last month
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- ☆88Updated 2 months ago
- A Video display simulator☆174Updated 7 months ago
- USB3 PIPE interface for Xilinx 7-Series☆238Updated 3 years ago