f4pga / prjurayLinks
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
☆80Updated 3 years ago
Alternatives and similar repositories for prjuray
Users that are interested in prjuray are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆147Updated 5 months ago
- Project X-Ray Database: XC7 Series☆73Updated 3 years ago
- ☆87Updated last month
- Bitstream relocation and manipulation tool.☆48Updated 2 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆125Updated 5 months ago
- Building and deploying container images for open source electronic design automation (EDA)☆116Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆68Updated 2 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- PicoRV☆43Updated 5 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- Experimental flows using nextpnr for Xilinx devices☆245Updated last year
- Naive Educational RISC V processor☆91Updated last month
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- VHDL library 4 FPGAs☆181Updated last week
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Experimental flows using nextpnr for Xilinx devices☆51Updated 5 months ago
- FPGA tool performance profiling☆103Updated last year
- Test of the USB3 IP Core from Daisho on a Xilinx device☆100Updated 6 years ago
- User-friendly explanation of Yosys options☆112Updated 4 years ago
- Generic Logic Interfacing Project☆47Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆34Updated 4 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆183Updated last year
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Spen's Official OpenOCD Mirror☆50Updated 8 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 9 months ago
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago