f4pga / prjurayLinks
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
☆80Updated 3 years ago
Alternatives and similar repositories for prjuray
Users that are interested in prjuray are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆146Updated 2 months ago
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- ☆79Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- A utility for Composing FPGA designs from Peripherals☆182Updated 7 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆122Updated 2 months ago
- Experimental flows using nextpnr for Xilinx devices☆245Updated 9 months ago
- Experimental flows using nextpnr for Xilinx devices☆49Updated last month
- Naive Educational RISC V processor☆85Updated 2 weeks ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆140Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆85Updated 3 weeks ago
- CoreScore☆159Updated 6 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆110Updated 2 years ago
- VHDL library 4 FPGAs☆181Updated this week
- Building and deploying container images for open source electronic design automation (EDA)☆115Updated 10 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 4 months ago
- PicoRV☆44Updated 5 years ago
- Demo SoC for SiliconCompiler.☆60Updated 2 months ago
- Xilinx Unisim Library in Verilog☆81Updated 5 years ago
- FPGA tool performance profiling☆102Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆152Updated 3 weeks ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆97Updated 2 years ago
- ☆47Updated 4 months ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ☆33Updated 2 years ago