Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
☆1,407Jan 5, 2026Updated 2 months ago
Alternatives and similar repositories for Silice
Users that are interested in Silice are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆710Updated this week
- Learning FPGA, yosys, nextpnr, and RISC-V☆3,427Nov 18, 2025Updated 4 months ago
- A modern hardware definition language and toolchain based on Python☆1,953Mar 16, 2026Updated last week
- SERV - The SErial RISC-V CPU☆1,766Feb 19, 2026Updated last month
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆756Jan 28, 2026Updated last month
- Build your hardware, easily!☆3,787Updated this week
- Universal utility for programming FPGA☆1,576Updated this week
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆464Sep 13, 2024Updated last year
- Multi-platform nightly builds of open source FPGA tools☆301Nov 3, 2021Updated 4 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,396Feb 13, 2026Updated last month
- Compact FPGA game console☆166Nov 14, 2023Updated 2 years ago
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆683Jan 8, 2022Updated 4 years ago
- Send video/audio over HDMI on an FPGA☆1,258Feb 3, 2024Updated 2 years ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆37Jul 2, 2023Updated 2 years ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- ECP5 breakout board in a feather physical format☆524Nov 6, 2024Updated last year
- Visual editor for open FPGA boards☆1,878Feb 16, 2026Updated last month
- Yosys Open SYnthesis Suite☆4,348Updated this week
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,004Updated this week
- nextpnr portable FPGA place and route tool☆1,631Updated this week
- CoreScore☆172Nov 14, 2025Updated 4 months ago
- An abstraction library for interfacing EDA tools☆754Mar 11, 2026Updated last week
- Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)☆259Aug 21, 2023Updated 2 years ago
- Documenting Lattice's 28nm FPGA parts☆149Feb 26, 2026Updated 3 weeks ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,075Feb 11, 2026Updated last month
- A Python toolbox for building complex digital hardware☆1,320Jan 5, 2026Updated 2 months ago
- Project Apicula 🐝: bitstream documentation for Gowin FPGAs☆648Mar 11, 2026Updated last week
- VHDL library 4 FPGAs☆185Mar 15, 2026Updated last week
- An attempt to recreate the RP2040 PIO in an FPGA☆313Jun 6, 2024Updated last year
- Documenting the Lattice ECP5 bit-stream format.☆448Feb 26, 2026Updated 3 weeks ago
- Hardware definition language that compiles to Verilog☆106Sep 26, 2021Updated 4 years ago
- Linux on LiteX-VexRiscv☆694Mar 6, 2026Updated 2 weeks ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆313May 25, 2023Updated 2 years ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆112Jul 20, 2024Updated last year
- Documenting the Xilinx 7-series bit-stream format.☆860Jun 5, 2025Updated 9 months ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆104Feb 17, 2023Updated 3 years ago
- A tutorial for using nmigen☆313Mar 17, 2021Updated 5 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,044Jun 27, 2024Updated last year
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆225Feb 19, 2026Updated last month