Alternatives and similar repositories for litex

Users that are interested in litex are comparing it to the libraries listed below

• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,993Updated last month
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,974Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,745Updated 3 weeks ago
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,535Updated this week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,919Updated last year
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,602Updated this week
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,320Updated 3 weeks ago
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,894Updated last week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,340Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,503Updated last month
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,480Updated 3 weeks ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,384Updated this week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,324Updated this week
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆4,261Updated this week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,913Updated last week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆682Updated last month
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,248Updated this week
• BrunoLevy / learn-fpga
  Learning FPGA, yosys, nextpnr, and RISC-V
  ☆3,384Updated 2 months ago
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,127Updated 4 months ago
• sylefeb / Silice
  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…
  ☆1,394Updated 3 weeks ago
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,776Updated last week
• FPGAwars / icestudio
  Visual editor for open FPGA boards
  ☆1,866Updated last month
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,751Updated this week
• hdl-util / hdmi
  Send video/audio over HDMI on an FPGA
  ☆1,246Updated 2 years ago
• FPGAwars / apio
  Open source ecosystem for open FPGA boards
  ☆948Updated this week
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆743Updated this week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,044Updated this week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,124Updated this week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,394Updated last year
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆682Updated 4 years ago