Alternatives and similar repositories for litex:

Users that are interested in litex are comparing it to the libraries listed below

• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,715Updated last month
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,528Updated 3 weeks ago
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,303Updated this week
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,264Updated 2 months ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,415Updated this week
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,668Updated last month
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,372Updated 2 months ago
• stnolting / neorv32
  A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …
  ☆1,724Updated last week
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆3,735Updated this week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,390Updated 9 months ago
• BrunoLevy / learn-fpga
  Learning FPGA, yosys, nextpnr, and RISC-V
  ☆2,748Updated last month
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,010Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,259Updated this week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆622Updated 2 weeks ago
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,046Updated last week
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,264Updated this week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆2,808Updated this week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,763Updated this week
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆668Updated 3 years ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆794Updated this week
• sylefeb / Silice
  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…
  ☆1,353Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆1,933Updated last week
• hdl-util / hdmi
  Send video/audio over HDMI on an FPGA
  ☆1,148Updated last year
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,509Updated this week
• myhdl / myhdl
  The MyHDL development repository
  ☆1,071Updated 2 months ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆969Updated this week
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,011Updated 2 months ago
• FPGAwars / apio
  Open source ecosystem for open FPGA boards
  ☆831Updated last week
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆634Updated 2 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,270Updated 11 months ago