Alternatives and similar repositories for litex

Users that are interested in litex are comparing it to the libraries listed below

• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,651Updated last week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,886Updated 2 months ago
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,866Updated this week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,434Updated last week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,526Updated this week
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,797Updated last month
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,306Updated 3 months ago
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆4,053Updated this week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,703Updated last year
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,180Updated this week
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,413Updated 2 months ago
• BrunoLevy / learn-fpga
  Learning FPGA, yosys, nextpnr, and RISC-V
  ☆2,952Updated 7 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,466Updated last month
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,093Updated last week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,345Updated 3 weeks ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,854Updated this week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆659Updated 3 weeks ago
• sylefeb / Silice
  Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…
  ☆1,378Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,635Updated 2 weeks ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,002Updated this week
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆727Updated 8 months ago
• FPGAwars / icestudio
  Visual editor for open FPGA boards
  ☆1,819Updated last month
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆677Updated last week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,082Updated this week
• hdl-util / hdmi
  Send video/audio over HDMI on an FPGA
  ☆1,202Updated last year
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆828Updated 3 months ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,102Updated this week
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,628Updated this week
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆679Updated 3 years ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,339Updated last year