Alternatives and similar repositories for sby

Users that are interested in sby are comparing it to the libraries listed below

• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆639Updated last month
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆602Updated 3 years ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆696Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆395Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆328Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆627Updated this week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆389Updated 5 months ago
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆533Updated last year
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆290Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆581Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆219Updated last week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆436Updated last week
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆282Updated last month
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆568Updated 2 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆335Updated 3 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆196Updated 3 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆286Updated 2 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆504Updated 4 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆320Updated 6 months ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆418Updated 3 weeks ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆709Updated last month
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆254Updated 3 months ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆298Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆803Updated 2 weeks ago
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆770Updated this week
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆580Updated 4 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆337Updated last week
• phanrahan / magma
  magma circuits
  ☆261Updated 8 months ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆242Updated this week