chipsalliance / fasm
FPGA Assembly (FASM) Parser and Generator
☆90Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for fasm
- Facilitates building open source tools for working with hardware description languages (HDLs)☆62Updated 4 years ago
- ☆52Updated 2 years ago
- The specification for the FIRRTL language☆46Updated this week
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 6 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- A SystemVerilog source file pickler.☆52Updated last month
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- FPGA tool performance profiling☆102Updated 9 months ago
- Naive Educational RISC V processor☆74Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- (System)Verilog to Chisel translator☆106Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆135Updated last month
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆80Updated 3 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆131Updated 3 weeks ago
- Mutation Cover with Yosys (MCY)☆77Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- ☆36Updated 2 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆71Updated 2 years ago
- Hardware generator debugger☆71Updated 9 months ago
- ☆75Updated last year
- ☆107Updated 3 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆134Updated 5 months ago
- FuseSoC standard core library☆115Updated last month
- A collection of big designs to run post-synthesis simulations with yosys☆47Updated 9 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 6 months ago
- Generic Register Interface (contains various adapters)☆100Updated last month