chipsalliance / fasmLinks
FPGA Assembly (FASM) Parser and Generator
☆99Updated 3 years ago
Alternatives and similar repositories for fasm
Users that are interested in fasm are comparing it to the libraries listed below
Sorting:
- The specification for the FIRRTL language☆62Updated this week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆59Updated 3 years ago
- FPGA tool performance profiling☆105Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Updated last month
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆107Updated 4 years ago
- Visual Simulation of Register Transfer Logic☆110Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆173Updated last week
- The multi-core cluster of a PULP system.☆111Updated last week
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- Mutation Cover with Yosys (MCY)☆90Updated 3 weeks ago
- Naive Educational RISC V processor☆94Updated 3 months ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184Updated 9 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆49Updated last month
- Demo SoC for SiliconCompiler.☆62Updated last week
- 😎 A curated list of awesome RISC-V implementations☆142Updated 2 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆113Updated 2 years ago
- ☆114Updated 5 years ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated this week
- Experiments with fixed function renderers and Chisel HDL☆60Updated 6 years ago
- Open-source FPGA research and prototyping framework.☆211Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆154Updated last year
- nextpnr portable FPGA place and route tool☆20Updated last year
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- SoftCPU/SoC engine-V☆55Updated 10 months ago