FPGA Assembly (FASM) Parser and Generator
☆104Jul 25, 2022Updated 4 years ago
Alternatives and similar repositories for fasm
Users that are interested in fasm are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Build Customized FPGA Implementations for Vivado☆389Updated this week
- A Verilog Synthesis Regression Test☆39Jan 19, 2026Updated 8 months ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆314Updated this week
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆86Feb 9, 2022Updated 4 years ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,267Updated this week
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- GUI for SymbiYosys☆18Aug 4, 2026Updated last month
- NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…☆19Dec 4, 2020Updated 5 years ago
- FOSS Flow For FPGA☆449Jan 6, 2025Updated last year
- Cross EDA Abstraction and Automation☆43Updated this week
- Documenting the Xilinx 7-series bit-stream format.☆914Jun 5, 2025Updated last year
- FPGA tool performance profiling☆108Feb 24, 2024Updated 2 years ago
- Experimental flows using nextpnr for Xilinx devices☆268Oct 11, 2024Updated last year
- Project X-Ray Database: XC7 Series☆77Dec 14, 2021Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Aug 24, 2026Updated 3 weeks ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆446Jul 1, 2021Updated 5 years ago
- Python interface to FPGA interchange format☆41Oct 19, 2022Updated 3 years ago
- ☆14Jun 21, 2026Updated 2 months ago
- A Freepascal library for sending SMS with Twilio☆15Aug 23, 2020Updated 6 years ago
- ☆62Jul 4, 2022Updated 4 years ago
- A LEF/DEF Utility.☆34Aug 15, 2019Updated 7 years ago
- SymbiFlow WIP changes for Yosys Open SYnthesis Suite☆42Mar 19, 2024Updated 2 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Bitstream Fault Analysis Tool☆16Jul 17, 2023Updated 3 years ago
- Wishbone bridge over SPI☆11Nov 13, 2019Updated 6 years ago
- nextpnr portable FPGA place and route tool☆1,754Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- A padring generator for ASICs☆26May 17, 2023Updated 3 years ago
- Implementation of the core of an exokernel-style operating system☆12Dec 6, 2014Updated 11 years ago
- Demo SoC for SiliconCompiler.☆64Jul 2, 2026Updated 2 months ago
- Yosys Open SYnthesis Suite☆4,761Updated this week
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆59Apr 8, 2023Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Tool for graphically viewing FPGA bitstream files and their connection to FASM features.☆19Apr 6, 2022Updated 4 years ago
- high abstraction synthesis☆14Apr 8, 2024Updated 2 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆18Jan 16, 2026Updated 8 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆85May 14, 2024Updated 2 years ago
- A Java framework focused on rapid prototyping of new CAD algorithms for FPGA compilation.☆25Dec 17, 2019Updated 6 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Documenting Lattice's 28nm FPGA parts☆154Jul 19, 2026Updated 2 months ago