Alternatives and similar repositories for RapidWright

Users that are interested in RapidWright are comparing it to the libraries listed below

• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆286Updated 3 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆257Updated 3 weeks ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆257Updated 3 weeks ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆279Updated 4 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆276Updated last year
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆598Updated 2 weeks ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆188Updated 2 years ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆338Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆582Updated 4 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆173Updated 9 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 6 months ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆201Updated 10 months ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆254Updated 3 months ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆140Updated 11 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆229Updated 3 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆221Updated 3 weeks ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆302Updated last month
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆107Updated 2 years ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆381Updated last month
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆173Updated 3 months ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆367Updated last week
• svunit / svunit
  ☆206Updated 5 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆438Updated 3 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆208Updated 5 months ago
• ferrandi / PandA-bambu
  PandA-bambu public repository
  ☆278Updated last month
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆407Updated 3 weeks ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆155Updated last month
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆282Updated 2 weeks ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆181Updated 8 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆115Updated last year