YosysHQ / icestorm
Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
☆1,041Updated last month
Alternatives and similar repositories for icestorm:
Users that are interested in icestorm are comparing it to the libraries listed below
- nextpnr portable FPGA place and route tool☆1,402Updated this week
- Open source ecosystem for open FPGA boards☆826Updated last week
- A Python toolbox for building complex digital hardware☆1,258Updated last month
- Place and route tool for FPGAs☆419Updated 5 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,252Updated last week
- Documenting the Xilinx 7-series bit-stream format.☆790Updated this week
- Documenting the Lattice ECP5 bit-stream format.☆410Updated 2 months ago
- Universal utility for programming FPGA☆1,281Updated this week
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆666Updated 3 years ago
- Multi-platform nightly builds of open source digital design and verification tools☆984Updated this week
- Small and low cost FPGA educational and development board☆589Updated last month
- Linux on LiteX-VexRiscv☆616Updated last week
- SERV - The SErial RISC-V CPU☆1,504Updated 2 weeks ago
- Yosys Open SYnthesis Suite☆3,690Updated this week
- Project Apicula 🐝: bitstream documentation for Gowin FPGAs☆541Updated last week
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆631Updated last month
- PCB for ULX3S FPGA R&D board☆386Updated last year
- VHDL synthesis (based on ghdl)☆326Updated last month
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆575Updated 4 years ago
- A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …☆1,698Updated this week
- ☆277Updated last year
- VHDL compiler and simulator☆672Updated this week
- A modern hardware definition language and toolchain based on Python☆1,653Updated 2 weeks ago
- A small, light weight, RISC CPU soft core☆1,367Updated last month
- VUnit is a unit testing framework for VHDL/SystemVerilog☆764Updated this week
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆633Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆429Updated last week
- Learn how to design digital systems and synthesize them into an FPGA using only opensource tools☆791Updated 4 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆647Updated 4 months ago
- ECP5 breakout board in a feather physical format☆497Updated 4 months ago