Alternatives and similar repositories for migen

Users that are interested in migen are comparing it to the libraries listed below

• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,367Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆836Updated 5 months ago
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆679Updated 3 years ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,561Updated this week
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,107Updated 2 months ago
• myhdl / myhdl
  The MyHDL development repository
  ☆1,101Updated 7 months ago
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,846Updated last month
• nickg / nvc
  VHDL compiler and simulator
  ☆756Updated this week
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆599Updated 4 months ago
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆433Updated last month
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,701Updated last month
• FPGAwars / apio
  Open source ecosystem for open FPGA boards
  ☆919Updated this week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,481Updated 3 weeks ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆800Updated last week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,250Updated this week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆724Updated 2 weeks ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆666Updated 2 months ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,108Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,480Updated 3 months ago
• YosysHQ / arachne-pnr
  Place and route tool for FPGAs
  ☆423Updated 6 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆676Updated 4 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆353Updated last month
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆683Updated last week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆459Updated this week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆566Updated 3 months ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,161Updated last week
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,619Updated this week
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆733Updated 10 months ago
• enjoy-digital / litepcie
  Small footprint and configurable PCIe core
  ☆642Updated 3 weeks ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,369Updated last year