Alternatives and similar repositories for migen:

Users that are interested in migen are comparing it to the libraries listed below

• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,044Updated last month
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,409Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,256Updated last week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆791Updated last week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,514Updated last week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆620Updated 2 weeks ago
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆666Updated 3 years ago
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,285Updated last week
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,215Updated last week
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,657Updated 3 weeks ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,368Updated last month
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,261Updated 10 months ago
• myhdl / myhdl
  The MyHDL development repository
  ☆1,068Updated 2 months ago
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆410Updated 2 months ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆957Updated this week
• nickg / nvc
  VHDL compiler and simulator
  ☆673Updated this week
• stnolting / neorv32
  A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …
  ☆1,702Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆1,922Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆526Updated last month
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆637Updated last week
• m-labs / misoc
  The original high performance and small footprint system-on-chip based on Migen™
  ☆321Updated last week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆670Updated this week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,699Updated last month
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆575Updated 4 years ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆766Updated this week
• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆631Updated 2 months ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,750Updated this week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆400Updated 2 months ago
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆989Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆647Updated 4 months ago