chipsalliance / f4pga-examplesLinks
Example designs showing different ways to use F4PGA toolchains.
☆277Updated last year
Alternatives and similar repositories for f4pga-examples
Users that are interested in f4pga-examples are comparing it to the libraries listed below
Sorting:
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆295Updated this week
- FOSS Flow For FPGA☆407Updated 8 months ago
- Multi-platform nightly builds of open source FPGA tools☆299Updated 3 years ago
- FuseSoC standard core library☆147Updated 4 months ago
- Experimental flows using nextpnr for Xilinx devices☆245Updated 11 months ago
- SoC based on VexRiscv and ICE40 UP5K☆160Updated 6 months ago
- A list of resources related to the open-source FPGA projects☆425Updated 2 years ago
- A simple, basic, formally verified UART controller☆311Updated last year
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- Example LED blinking project for your FPGA dev board of choice☆185Updated 3 weeks ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆349Updated 7 months ago
- A curated list of awesome resources for HDL design and verification☆158Updated last week
- A huge VHDL library for FPGA and digital ASIC development☆401Updated this week
- VHDL synthesis (based on ghdl)☆346Updated 4 months ago
- A simple RISC-V processor for use in FPGA designs.☆279Updated last year
- Fabric generator and CAD tools.☆198Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆233Updated 3 weeks ago
- Small footprint and configurable DRAM core☆436Updated 3 months ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆217Updated 3 weeks ago
- Documenting the Lattice ECP5 bit-stream format.☆427Updated 2 weeks ago
- VeeR EL2 Core☆297Updated this week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- LiteX boards files☆434Updated last week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆217Updated 11 months ago
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆284Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆324Updated 9 months ago
- ☆348Updated 2 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆116Updated 4 years ago
- CORE-V Family of RISC-V Cores☆299Updated 7 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago