Alternatives and similar repositories for f4pga-examples

Users that are interested in f4pga-examples are comparing it to the libraries listed below

• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆299Updated this week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆252Updated last year
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆417Updated last year
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆299Updated 4 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆370Updated 10 months ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆189Updated 3 weeks ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆160Updated 9 months ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆447Updated this week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆319Updated last year
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆435Updated 3 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆315Updated 10 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆354Updated last week
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆283Updated last year
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆459Updated last year
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆242Updated 4 months ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆166Updated last week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆462Updated 3 weeks ago
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆223Updated last year
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆436Updated 2 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated last week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆336Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆310Updated last week
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆284Updated 6 years ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆419Updated 2 weeks ago
• litex-hub / litex-boards
  LiteX boards files
  ☆452Updated last week
• olofk / corescore
  CoreScore
  ☆171Updated last month
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆282Updated 5 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆184Updated this week