Alternatives and similar repositories for f4pga-examples

Users that are interested in f4pga-examples are comparing it to the libraries listed below

• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆290Updated last week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆394Updated 6 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆244Updated 9 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 3 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆306Updated last year
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆297Updated 3 years ago
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆416Updated 2 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆391Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆144Updated last month
• litex-hub / litex-boards
  LiteX boards files
  ☆420Updated last week
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆277Updated 10 months ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆178Updated last month
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆338Updated 4 months ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆426Updated last week
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆435Updated 10 months ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆153Updated this week
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆336Updated last month
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆420Updated 2 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆278Updated 5 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆321Updated 7 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆190Updated this week
• efabless / OpenLane
  This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …
  ☆152Updated last year
• mattvenn / awesome-opensource-asic-resources
  ☆333Updated 2 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆221Updated 2 weeks ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆311Updated 4 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆201Updated 4 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆572Updated 3 months ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆402Updated 2 months ago
• damdoy / ice40_ultraplus_examples
  Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
  ☆273Updated last year