chipsalliance / f4pga-examplesLinks
Example designs showing different ways to use F4PGA toolchains.
☆276Updated last year
Alternatives and similar repositories for f4pga-examples
Users that are interested in f4pga-examples are comparing it to the libraries listed below
Sorting:
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆295Updated last week
- Experimental flows using nextpnr for Xilinx devices☆246Updated last year
- FOSS Flow For FPGA☆409Updated 9 months ago
- FuseSoC standard core library☆147Updated 4 months ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago
- Fabric generator and CAD tools.☆197Updated last week
- Multi-platform nightly builds of open source FPGA tools☆299Updated 3 years ago
- A simple, basic, formally verified UART controller☆311Updated last year
- A curated list of awesome resources for HDL design and verification☆162Updated last week
- A huge VHDL library for FPGA and digital ASIC development☆403Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆356Updated 7 months ago
- VHDL synthesis (based on ghdl)☆347Updated 2 weeks ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆234Updated last month
- A list of resources related to the open-source FPGA projects☆424Updated 2 years ago
- A simple RISC-V processor for use in FPGA designs.☆279Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆218Updated this week
- LiteX boards files☆440Updated last week
- Small footprint and configurable DRAM core☆444Updated last week
- Example LED blinking project for your FPGA dev board of choice☆185Updated last week
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆158Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- Small footprint and configurable Ethernet core☆265Updated last week
- CoreScore☆164Updated 2 months ago
- A 32-bit RISC-V soft processor☆315Updated 3 months ago
- CORE-V Family of RISC-V Cores☆302Updated 8 months ago
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆284Updated last year
- Documenting the Lattice ECP5 bit-stream format.☆428Updated last month
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆117Updated 4 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆219Updated 11 months ago