openXC7 / nextpnr-xilinxLinks
Experimental flows using nextpnr for Xilinx devices
☆54Updated last month
Alternatives and similar repositories for nextpnr-xilinx
Users that are interested in nextpnr-xilinx are comparing it to the libraries listed below
Sorting:
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆91Updated 6 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆58Updated last month
- ☆71Updated last year
- Nitro USB FPGA core☆85Updated last year
- Generate Zynq configurations without using the vendor GUI☆30Updated 2 years ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆64Updated 7 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆73Updated last week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated last week
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆81Updated 2 months ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- assorted library of utility cores for amaranth HDL☆97Updated last year
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆186Updated last year
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102Updated 2 years ago
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- ☆88Updated 2 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆92Updated 7 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- VHDL library 4 FPGAs☆182Updated this week
- Nix flake for openXC7☆43Updated 8 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆81Updated 3 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆70Updated 3 years ago
- FuseSoC standard core library☆150Updated 2 weeks ago
- Naive Educational RISC V processor☆92Updated 2 months ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆82Updated last year
- Board definitions for Amaranth HDL☆121Updated 3 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆112Updated last year
- CoreScore☆171Updated last month
- Experimental flows using nextpnr for Xilinx devices☆250Updated last year