Project Apicula 🐝: bitstream documentation for Gowin FPGAs
☆706Nov 6, 2026Updated this week
Alternatives and similar repositories for apicula
Users that are interested in apicula are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Universal utility for programming FPGA☆1,785Updated this week
- nextpnr portable FPGA place and route tool☆1,787Updated this week
- Documenting the Lattice ECP5 bit-stream format.☆477Updated this week
- Documenting Lattice's 28nm FPGA parts☆155Jul 19, 2026Updated 3 months ago
- Multi-platform nightly builds of open source digital design and verification tools☆1,806Updated this week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Documenting the Anlogic FPGA bit-stream format.☆92Dec 25, 2022Updated 3 years ago
- Yosys Open SYnthesis Suite☆4,872Updated this week
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,193Updated this week
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 5 years ago
- Build your hardware, easily!☆4,190Updated this week
- A modern hardware definition language and toolchain based on Python☆2,125Sep 18, 2026Updated last month
- SERV - The SErial RISC-V CPU☆1,916Aug 25, 2026Updated 2 months ago
- Experimental flows using nextpnr for Xilinx devices☆271Oct 11, 2024Updated 2 years ago
- Documenting the Xilinx 7-series bit-stream format.☆927Jun 5, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards☆461Jun 20, 2025Updated last year
- Linsn RV901T HUB75 LED "Receiver Card" Reverse Engineering☆649May 30, 2025Updated last year
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pi…☆1,431Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,398Sep 7, 2026Updated 2 months ago
- LiteX boards files☆508Updated this week
- Miscellaneous ULX3S examples (advanced)☆87Feb 7, 2026Updated 9 months ago
- Examples for the Lushay Labs tang nano 9k series☆151Jun 12, 2024Updated 2 years ago
- Visual editor for open FPGA boards☆1,945Oct 18, 2026Updated 2 weeks ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆48Oct 19, 2026Updated 2 weeks ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)☆262Aug 21, 2023Updated 3 years ago
- Learning FPGA, yosys, nextpnr, and RISC-V☆3,754Oct 30, 2026Updated last week
- PCB for ULX3S FPGA R&D board☆469Apr 27, 2025Updated last year
- Open source ecosystem for open FPGA boards☆1,024Updated this week
- RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card☆55Oct 15, 2026Updated 3 weeks ago
- 3-stage RV32IMACZb* processor with debug☆1,131Aug 29, 2026Updated 2 months ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆37Jul 2, 2023Updated 3 years ago
- iCESugar FPGA Board (base on iCE40UP5k)☆463Jul 31, 2026Updated 3 months ago
- ECP5 breakout board in a feather physical format☆546Nov 6, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ECPDAP allows you to program ECP5 FPGAs and attached SPI flash using CMSIS-DAP probes in JTAG mode.☆75Jul 4, 2026Updated 4 months ago
- An attempt to recreate the RP2040 PIO in an FPGA☆323Jun 6, 2024Updated 2 years ago
- Cyclone V bitstream reverse-engineering project☆140Updated this week
- 32-bit RISC-V system on chip for iCE40 FPGAs☆313May 25, 2023Updated 3 years ago
- ☆23Oct 19, 2021Updated 5 years ago
- CH55x USB to JTAG bridge☆149Mar 12, 2025Updated last year
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,303Oct 13, 2026Updated 3 weeks ago