chipsalliance / f4pgaLinks
FOSS Flow For FPGA
☆415Updated 11 months ago
Alternatives and similar repositories for f4pga
Users that are interested in f4pga are comparing it to the libraries listed below
Sorting:
- Example designs showing different ways to use F4PGA toolchains.☆281Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆298Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆481Updated last week
- SystemVerilog to Verilog conversion☆681Updated 3 weeks ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆369Updated 9 months ago
- Experimental flows using nextpnr for Xilinx devices☆248Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆430Updated 3 months ago
- Small footprint and configurable DRAM core☆460Updated 2 weeks ago
- A dependency management tool for hardware projects.☆337Updated this week
- CORE-V Family of RISC-V Cores☆310Updated 10 months ago
- An abstraction library for interfacing EDA tools☆729Updated last month
- A list of resources related to the open-source FPGA projects☆433Updated 3 years ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆321Updated 2 weeks ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆450Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆351Updated this week
- VHDL synthesis (based on ghdl)☆353Updated last month
- A Linux-capable RISC-V multicore for and by the world☆749Updated last month
- SystemVerilog synthesis tool☆220Updated 9 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆221Updated last year
- A huge VHDL library for FPGA and digital ASIC development☆413Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆307Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆332Updated last year
- ☆301Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆624Updated last week
- Fabric generator and CAD tools.☆214Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆548Updated last month
- Bus bridges and other odds and ends☆610Updated 8 months ago
- ☆364Updated 2 years ago
- VeeR EL2 Core☆310Updated this week