Alternatives and similar repositories for f4pga:

Users that are interested in f4pga are comparing it to the libraries listed below

• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆272Updated 11 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆604Updated this week
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆280Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆431Updated last week
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆326Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆590Updated this week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆246Updated last month
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆560Updated this week
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆380Updated this week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆400Updated 2 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆670Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆382Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆526Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆669Updated 3 weeks ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆228Updated 5 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆320Updated 3 weeks ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆212Updated this week
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆326Updated this week
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆410Updated 2 months ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆420Updated 6 months ago
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆637Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆309Updated this week
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆602Updated this week
• mattvenn / awesome-opensource-asic-resources
  ☆314Updated last year
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆989Updated this week
• SpinalHDL / NaxRiscv
  ☆279Updated last week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆620Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆461Updated last month
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆205Updated 4 months ago
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆401Updated 2 years ago