Documenting Lattice's 28nm FPGA parts
☆149Feb 26, 2026Updated 3 weeks ago
Alternatives and similar repositories for prjoxide
Users that are interested in prjoxide are comparing it to the libraries listed below
Sorting:
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102May 16, 2023Updated 2 years ago
- Documenting the Lattice ECP5 bit-stream format.☆448Feb 26, 2026Updated 3 weeks ago
- Experimental flows using nextpnr for Xilinx devices☆255Oct 11, 2024Updated last year
- Documenting the Microchip (Atmel) ATF15xx CPLD fuse maps and programming algorithms☆59Jun 10, 2025Updated 9 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆82Feb 9, 2022Updated 4 years ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆683Jan 8, 2022Updated 4 years ago
- Small footprint and configurable HyperBus core☆14Jul 6, 2022Updated 3 years ago
- 妖刀夢渡☆63Apr 2, 2019Updated 6 years ago
- nextpnr portable FPGA place and route tool☆1,631Updated this week
- ☆64Jul 21, 2020Updated 5 years ago
- Low-cost ECP5 FPGA development board☆80Sep 1, 2020Updated 5 years ago
- Experiments with Yosys cxxrtl backend☆50Jan 16, 2025Updated last year
- Hot Reconfiguration Technology demo☆42Aug 23, 2022Updated 3 years ago
- basic example of litex on colorLight 5A-75B based on fpga_101/lab004☆38Jan 11, 2023Updated 3 years ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆94Mar 12, 2026Updated last week
- Board definitions for Amaranth HDL☆125Mar 13, 2026Updated last week
- Betrusted embedded controller (UP5K)☆49Dec 22, 2023Updated 2 years ago
- KiCad bus length matching script.☆30Jun 16, 2024Updated last year
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 3 years ago
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆88Oct 29, 2019Updated 6 years ago
- ECP5 breakout board in a feather physical format☆524Nov 6, 2024Updated last year
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Dec 6, 2021Updated 4 years ago
- Tool to fix FT2232's uart interface configuration for ecp5evn (LFE5UM5G-85F-EVN) board☆12Jun 17, 2021Updated 4 years ago
- LiteX project for the ButterStick bootloader☆14Mar 13, 2023Updated 3 years ago
- My pergola FPGA projects☆30Jun 23, 2021Updated 4 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆93Nov 7, 2024Updated last year
- Cyclone V bitstream reverse-engineering project☆131Oct 19, 2023Updated 2 years ago
- Project Apicula 🐝: bitstream documentation for Gowin FPGAs☆648Mar 11, 2026Updated last week
- [MIGRATED to https://codeberg.org/prjunnamed/prjcombine/] An FPGA reverse engineering and documentation project☆66Mar 12, 2026Updated last week
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 9 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Aug 20, 2022Updated 3 years ago
- A 32-bit RISC-V soft processor☆322Jan 26, 2026Updated last month
- MIPI testing with LiteX on CrossLink-NX☆14Jan 29, 2026Updated last month
- ☆16Jun 13, 2021Updated 4 years ago
- A modern hardware definition language and toolchain based on Python☆1,953Updated this week
- Logicbone ECP5 Development Board☆123Jun 27, 2020Updated 5 years ago
- ☆17Aug 16, 2023Updated 2 years ago
- ☆12Jun 4, 2021Updated 4 years ago