Alternatives and similar repositories for edalize

Users that are interested in edalize are comparing it to the libraries listed below

• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆593Updated 6 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆670Updated 4 months ago
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆596Updated 2 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆475Updated 2 weeks ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,344Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆612Updated 2 weeks ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆409Updated 3 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆665Updated 3 weeks ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆422Updated last month
• pyuvm / pyuvm
  The UVM written in Python
  ☆464Updated last week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆956Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆460Updated 4 months ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆403Updated last week
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆347Updated 2 weeks ago
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆560Updated 2 years ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆344Updated this week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,011Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆532Updated last month
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆792Updated 2 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆444Updated 5 months ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆653Updated last month
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆409Updated 9 months ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆447Updated last year
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆295Updated last week
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆424Updated 2 years ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆250Updated 3 weeks ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆427Updated last month
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆356Updated 7 months ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆282Updated 5 years ago