An abstraction library for interfacing EDA tools
☆771Apr 24, 2026Updated last month
Alternatives and similar repositories for edalize
Users that are interested in edalize are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Package manager and build abstraction tool for FPGA/ASIC development☆1,420Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆463May 31, 2026Updated 2 weeks ago
- cocotb: Python-based chip (RTL) verification☆2,399Updated this week
- SystemVerilog compiler and language services☆1,068Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆258May 31, 2026Updated 2 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,858Updated this week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆328Jun 30, 2025Updated 11 months ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆828May 14, 2026Updated last month
- SERV - The SErial RISC-V CPU☆1,812Feb 19, 2026Updated 3 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆378Updated this week
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- An Open-source FPGA IP Generator☆1,111Updated this week
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆102Jan 30, 2025Updated last year
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,824Mar 25, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A dependency management tool for hardware projects.☆375Updated this week
- SystemVerilog to Verilog conversion☆736Mar 28, 2026Updated 2 months ago
- A Python toolbox for building complex digital hardware☆1,327Jan 5, 2026Updated 5 months ago
- Universal utility for programming FPGA☆1,651Jun 4, 2026Updated last week
- Modular hardware build system☆1,165Updated this week
- Yosys Open SYnthesis Suite☆4,513Updated this week
- Code generation tool for control and status registers☆463May 30, 2026Updated 2 weeks ago
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆475Updated this week
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Building and deploying container images for open source electronic design automation (EDA)☆122Oct 3, 2024Updated last year
- FuseSoC standard core library☆165Apr 28, 2026Updated last month
- A modern hardware definition language and toolchain based on Python☆2,028May 25, 2026Updated 2 weeks ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆225May 19, 2026Updated 3 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆669May 11, 2026Updated last month
- Hardware Description Languages☆1,151Apr 6, 2026Updated 2 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆322Mar 6, 2026Updated 3 months ago
- Build Customized FPGA Implementations for Vivado☆381Updated this week
- Documenting the Xilinx 7-series bit-stream format.☆893Jun 5, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- VHDL synthesis (based on ghdl)☆366May 14, 2026Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,593Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,907Jun 3, 2026Updated last week
- draws an SVG schematic from a JSON netlist☆796Jan 25, 2024Updated 2 years ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆468Sep 13, 2024Updated last year
- nextpnr portable FPGA place and route tool☆1,694Jun 5, 2026Updated last week
- magma circuits☆263Oct 19, 2024Updated last year