An abstraction library for interfacing EDA tools
☆762Apr 24, 2026Updated last week
Alternatives and similar repositories for edalize
Users that are interested in edalize are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Package manager and build abstraction tool for FPGA/ASIC development☆1,410Feb 13, 2026Updated 2 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆458Apr 5, 2026Updated last month
- cocotb: Python-based chip (RTL) verification☆2,354Apr 27, 2026Updated last week
- SystemVerilog compiler and language services☆1,027Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆255Feb 22, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,834Mar 13, 2026Updated last month
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆323Jun 30, 2025Updated 10 months ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆826Apr 22, 2026Updated last week
- SERV - The SErial RISC-V CPU☆1,791Feb 19, 2026Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆375Updated this week
- SystemVerilog synthesis tool☆232Mar 10, 2025Updated last year
- An Open-source FPGA IP Generator☆1,094Updated this week
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆102Jan 30, 2025Updated last year
- A dependency management tool for hardware projects.☆365Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,769Mar 25, 2026Updated last month
- SystemVerilog to Verilog conversion☆725Mar 28, 2026Updated last month
- A Python toolbox for building complex digital hardware☆1,322Jan 5, 2026Updated 4 months ago
- Universal utility for programming FPGA☆1,615Apr 26, 2026Updated last week
- Modular hardware build system☆1,156Updated this week
- Yosys Open SYnthesis Suite☆4,423Updated this week
- FuseSoC standard core library☆162Updated this week
- UVM 1.2 port to Python☆260Feb 9, 2025Updated last year
- Code generation tool for control and status registers☆455Apr 19, 2026Updated 2 weeks ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆470Mar 30, 2026Updated last month
- Building and deploying container images for open source electronic design automation (EDA)☆121Oct 3, 2024Updated last year
- A modern hardware definition language and toolchain based on Python☆2,005Updated this week
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆224Dec 23, 2025Updated 4 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆660Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆315Mar 6, 2026Updated last month
- Hardware Description Languages☆1,141Apr 6, 2026Updated 3 weeks ago
- Build Customized FPGA Implementations for Vivado☆371Updated this week
- Documenting the Xilinx 7-series bit-stream format.☆875Jun 5, 2025Updated 11 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,566Apr 22, 2026Updated last week
- VHDL synthesis (based on ghdl)☆359Mar 14, 2026Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,864Apr 14, 2026Updated 3 weeks ago
- draws an SVG schematic from a JSON netlist☆789Jan 25, 2024Updated 2 years ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆465Sep 13, 2024Updated last year
- nextpnr portable FPGA place and route tool☆1,658Updated this week
- magma circuits☆265Oct 19, 2024Updated last year