olofk / edalize

Related projects: ⓘ

• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆535Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆494Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆498Updated 2 weeks ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆389Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆353Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆470Updated 8 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,164Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆284Updated this week
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆480Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆357Updated this week
• pyuvm / pyuvm
  The UVM written in Python
  ☆358Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆418Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆597Updated 2 weeks ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆270Updated this week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆350Updated last month
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆376Updated last month
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,048Updated last month
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆425Updated 2 weeks ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆301Updated 2 months ago
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆321Updated this week
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆539Updated 3 years ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆812Updated 2 months ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆266Updated 4 years ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆226Updated 2 weeks ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆359Updated last month
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆387Updated this week
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆281Updated 2 weeks ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆221Updated 2 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆438Updated 5 months ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆723Updated this week