An abstraction library for interfacing EDA tools
☆755Feb 18, 2026Updated 2 weeks ago
Alternatives and similar repositories for edalize
Users that are interested in edalize are comparing it to the libraries listed below
Sorting:
- Package manager and build abstraction tool for FPGA/ASIC development☆1,389Feb 13, 2026Updated 2 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆449Feb 23, 2026Updated last week
- SystemVerilog compiler and language services☆961Feb 25, 2026Updated last week
- cocotb: Python-based chip (RTL) verification☆2,266Updated this week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆317Jun 30, 2025Updated 8 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆250Feb 22, 2026Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,776Dec 22, 2025Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆360Updated this week
- An Open-source FPGA IP Generator☆1,056Updated this week
- SERV - The SErial RISC-V CPU☆1,757Feb 19, 2026Updated last week
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,717Sep 15, 2025Updated 5 months ago
- SystemVerilog synthesis tool☆228Mar 10, 2025Updated 11 months ago
- SystemVerilog to Verilog conversion☆704Nov 24, 2025Updated 3 months ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆818Updated this week
- A dependency management tool for hardware projects.☆349Updated this week
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Jan 30, 2025Updated last year
- A Python toolbox for building complex digital hardware☆1,322Jan 5, 2026Updated last month
- Universal utility for programming FPGA☆1,554Updated this week
- UVM 1.2 port to Python☆259Feb 9, 2025Updated last year
- Yosys Open SYnthesis Suite☆4,305Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆463Nov 4, 2025Updated 4 months ago
- VHDL synthesis (based on ghdl)☆356Jan 11, 2026Updated last month
- Build Customized FPGA Implementations for Vivado☆355Feb 19, 2026Updated last week
- magma circuits☆265Oct 19, 2024Updated last year
- A modern hardware definition language and toolchain based on Python☆1,910Feb 16, 2026Updated 2 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆649Jan 19, 2026Updated last month
- Building and deploying container images for open source electronic design automation (EDA)☆121Oct 3, 2024Updated last year
- Code generation tool for control and status registers☆448Jan 7, 2026Updated last month
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆221Dec 23, 2025Updated 2 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,510Updated this week
- Modular hardware build system☆1,130Updated this week
- nextpnr portable FPGA place and route tool☆1,623Updated this week
- Hardware Description Languages☆1,115Jul 14, 2025Updated 7 months ago
- An open-source static random access memory (SRAM) compiler.☆1,012Jan 16, 2026Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆313Feb 20, 2026Updated last week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,208Updated this week
- Documenting the Xilinx 7-series bit-stream format.☆851Jun 5, 2025Updated 8 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,774Feb 17, 2026Updated 2 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆769Feb 9, 2026Updated 3 weeks ago