An abstraction library for interfacing EDA tools
☆757Apr 1, 2026Updated 2 weeks ago
Alternatives and similar repositories for edalize
Users that are interested in edalize are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Package manager and build abstraction tool for FPGA/ASIC development☆1,407Feb 13, 2026Updated 2 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆457Apr 5, 2026Updated last week
- cocotb: Python-based chip (RTL) verification☆2,316Updated this week
- SystemVerilog compiler and language services☆1,000Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆256Feb 22, 2026Updated last month
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,807Mar 13, 2026Updated last month
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆321Jun 30, 2025Updated 9 months ago
- SERV - The SErial RISC-V CPU☆1,779Feb 19, 2026Updated last month
- Test suite designed to check compliance with the SystemVerilog standard.☆371Apr 7, 2026Updated last week
- SystemVerilog synthesis tool☆232Mar 10, 2025Updated last year
- VUnit is a unit testing framework for VHDL/SystemVerilog☆821Updated this week
- An Open-source FPGA IP Generator☆1,079Updated this week
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆102Jan 30, 2025Updated last year
- A dependency management tool for hardware projects.☆361Updated this week
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,749Mar 25, 2026Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆719Mar 28, 2026Updated 2 weeks ago
- A Python toolbox for building complex digital hardware☆1,321Jan 5, 2026Updated 3 months ago
- Universal utility for programming FPGA☆1,590Updated this week
- Modular hardware build system☆1,143Updated this week
- Yosys Open SYnthesis Suite☆4,397Updated this week
- UVM 1.2 port to Python☆260Feb 9, 2025Updated last year
- FuseSoC standard core library☆161Mar 11, 2026Updated last month
- Code generation tool for control and status registers☆452Apr 2, 2026Updated last week
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆471Mar 30, 2026Updated 2 weeks ago
- Building and deploying container images for open source electronic design automation (EDA)☆121Oct 3, 2024Updated last year
- A modern hardware definition language and toolchain based on Python☆1,987Updated this week
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆223Dec 23, 2025Updated 3 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆661Apr 7, 2026Updated last week
- Hardware Description Languages☆1,141Apr 6, 2026Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆315Mar 6, 2026Updated last month
- Build Customized FPGA Implementations for Vivado☆367Apr 7, 2026Updated last week
- Documenting the Xilinx 7-series bit-stream format.☆869Jun 5, 2025Updated 10 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,546Updated this week
- VHDL synthesis (based on ghdl)☆357Mar 14, 2026Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,836Updated this week
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆465Sep 13, 2024Updated last year
- draws an SVG schematic from a JSON netlist☆783Jan 25, 2024Updated 2 years ago
- nextpnr portable FPGA place and route tool☆1,647Updated this week
- An open-source static random access memory (SRAM) compiler.☆1,039Updated this week