Alternatives and similar repositories for yosys

Users that are interested in yosys are comparing it to the libraries listed below

• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,593Updated last week
• steveicarus / iverilog
  Icarus Verilog
  ☆3,282Updated last week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,282Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,218Updated this week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,979Updated last month
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,325Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,381Updated 3 weeks ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,726Updated last week
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,128Updated 3 months ago
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,682Updated this week
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,737Updated 3 weeks ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,184Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,500Updated last month
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆890Updated 2 weeks ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,889Updated last year
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,516Updated last week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,903Updated last week
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,958Updated this week
• ghdl / ghdl
  VHDL 2008/93/87 simulator
  ☆2,725Updated this week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,385Updated last year
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,735Updated 3 weeks ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆810Updated last week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,049Updated this week
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,466Updated last week
• The-OpenROAD-Project / OpenLane
  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…
  ☆1,669Updated 4 months ago
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,320Updated last week
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,885Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆846Updated 7 months ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,119Updated last week
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,755Updated this week