YosysHQ / yosysLinks
Yosys Open SYnthesis Suite
☆4,198Updated this week
Alternatives and similar repositories for yosys
Users that are interested in yosys are comparing it to the libraries listed below
Sorting:
- nextpnr portable FPGA place and route tool☆1,574Updated this week
- Icarus Verilog☆3,257Updated last week
- Verilator open-source SystemVerilog simulator and lint system☆3,244Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,951Updated last week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,856Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,376Updated last week
- Multi-platform nightly builds of open source digital design and verification tools☆1,281Updated last week
- cocotb: Python-based chip (RTL) verification☆2,197Updated this week
- SERV - The SErial RISC-V CPU☆1,711Updated last week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,179Updated this week
- A small, light weight, RISC CPU soft core☆1,490Updated 2 weeks ago
- Scala based HDL☆1,897Updated this week
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,935Updated this week
- Build your hardware, easily!☆3,645Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,712Updated this week
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,117Updated 3 months ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆878Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,718Updated 2 weeks ago
- Universal utility for programming FPGA☆1,498Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,040Updated 3 weeks ago
- A Python toolbox for building complex digital hardware☆1,319Updated 2 months ago
- Verilog library for ASIC and FPGA designers☆1,377Updated last year
- Documenting the Xilinx 7-series bit-stream format.☆842Updated 6 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,456Updated 5 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,075Updated last week
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,654Updated 3 months ago
- Modular hardware build system☆1,113Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,733Updated this week
- VUnit is a unit testing framework for VHDL/SystemVerilog☆805Updated last week
- An Open-source FPGA IP Generator☆1,029Updated this week