YosysHQ / yosysLinks
Yosys Open SYnthesis Suite
☆3,953Updated this week
Alternatives and similar repositories for yosys
Users that are interested in yosys are comparing it to the libraries listed below
Sorting:
- Verilator open-source SystemVerilog simulator and lint system☆3,016Updated this week
- nextpnr portable FPGA place and route tool☆1,483Updated this week
- Icarus Verilog☆3,112Updated 2 weeks ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,834Updated last month
- Multi-platform nightly builds of open source digital design and verification tools☆1,119Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,603Updated last year
- cocotb: Python-based chip (RTL) verification☆2,050Updated this week
- Scala based HDL☆1,833Updated this week
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,128Updated this week
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,086Updated 2 months ago
- SERV - The SErial RISC-V CPU☆1,617Updated 2 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,318Updated last month
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,601Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,568Updated last week
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆809Updated last month
- A small, light weight, RISC CPU soft core☆1,438Updated 5 months ago
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆1,823Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,595Updated last week
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,546Updated 3 weeks ago
- VHDL 2008/93/87 simulator☆2,602Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,944Updated 2 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,378Updated 2 weeks ago
- Universal utility for programming FPGA☆1,377Updated last week
- VUnit is a unit testing framework for VHDL/SystemVerilog☆784Updated 2 months ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,087Updated this week
- Hardware Description Languages☆1,050Updated 3 weeks ago
- Verilog library for ASIC and FPGA designers☆1,322Updated last year
- Build your hardware, easily!☆3,429Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,922Updated this week
- VHDL compiler and simulator☆721Updated this week