YosysHQ / yosysLinks
Yosys Open SYnthesis Suite
☆3,832Updated this week
Alternatives and similar repositories for yosys
Users that are interested in yosys are comparing it to the libraries listed below
Sorting:
- nextpnr portable FPGA place and route tool☆1,444Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆2,925Updated this week
- Icarus Verilog☆3,061Updated 2 weeks ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,062Updated 2 months ago
- cocotb: Python-based chip (RTL) verification☆1,986Updated this week
- A Python toolbox for building complex digital hardware☆1,275Updated 3 weeks ago
- Multi-platform nightly builds of open source digital design and verification tools☆1,059Updated this week
- SERV - The SErial RISC-V CPU☆1,589Updated 2 weeks ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,103Updated this week
- Build your hardware, easily!☆3,333Updated this week
- Verilog library for ASIC and FPGA designers☆1,289Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,293Updated this week
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆782Updated 3 weeks ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,506Updated 11 months ago
- Universal utility for programming FPGA☆1,331Updated this week
- A small, light weight, RISC CPU soft core☆1,409Updated 3 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,547Updated 2 weeks ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,545Updated this week
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,494Updated 3 months ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆775Updated 3 weeks ago
- Scala based HDL☆1,794Updated this week
- VHDL compiler and simulator☆696Updated this week
- Documenting the Xilinx 7-series bit-stream format.☆801Updated 2 weeks ago
- SystemVerilog compiler and language services☆755Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,775Updated last month
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,487Updated this week
- A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …☆1,770Updated this week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆667Updated 6 months ago
- An open-source static random access memory (SRAM) compiler.☆906Updated last month
- An open-source microcontroller system based on RISC-V☆956Updated last year