Alternatives and similar repositories for yosys:

Users that are interested in yosys are comparing it to the libraries listed below

• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,402Updated last week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆2,760Updated this week
• steveicarus / iverilog
  Icarus Verilog
  ☆2,981Updated last week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,062Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,252Updated last week
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,041Updated last month
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆724Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆1,917Updated this week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,694Updated last month
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,367Updated last month
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,352Updated 8 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,504Updated 2 weeks ago
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆984Updated this week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,741Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,491Updated 3 weeks ago
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,653Updated 2 weeks ago
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,492Updated last month
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,258Updated last month
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆790Updated this week
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,008Updated last month
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,258Updated 10 months ago
• nickg / nvc
  VHDL compiler and simulator
  ☆672Updated this week
• stnolting / neorv32
  A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …
  ☆1,698Updated this week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆881Updated 4 months ago
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,243Updated this week
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,201Updated this week
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆633Updated this week
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆686Updated 9 months ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆764Updated last week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆697Updated this week