Alternatives and similar repositories for yosys

Users that are interested in yosys are comparing it to the libraries listed below

• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,494Updated this week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,036Updated this week
• steveicarus / iverilog
  Icarus Verilog
  ☆3,120Updated 3 weeks ago
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,137Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,630Updated 2 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,325Updated this week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,629Updated last year
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,846Updated last month
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,058Updated last week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,132Updated this week
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,089Updated 2 months ago
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,615Updated last week
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,456Updated 2 weeks ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,449Updated 2 weeks ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,609Updated 2 weeks ago
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,390Updated 2 weeks ago
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,301Updated 2 months ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,840Updated this week
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,831Updated last week
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆816Updated 2 months ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆818Updated 2 months ago
• ghdl / ghdl
  VHDL 2008/93/87 simulator
  ☆2,612Updated this week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆981Updated last week
• The-OpenROAD-Project / OpenLane
  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…
  ☆1,560Updated last month
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆784Updated last week
• nickg / nvc
  VHDL compiler and simulator
  ☆729Updated this week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,063Updated this week
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,956Updated 3 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,330Updated last year
• openhwgroup / cva6
  The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…
  ☆2,588Updated last week