Alternatives and similar repositories for yosys

Users that are interested in yosys are comparing it to the libraries listed below

• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,457Updated this week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆2,946Updated this week
• steveicarus / iverilog
  Icarus Verilog
  ☆3,071Updated last month
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,069Updated 2 weeks ago
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,537Updated 11 months ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,110Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,081Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,600Updated 2 weeks ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,803Updated last week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,420Updated 4 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,568Updated last week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,357Updated this week
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆789Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,300Updated 2 weeks ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,009Updated this week
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,560Updated last week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆911Updated 2 months ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,799Updated this week
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,278Updated last week
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,714Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆803Updated 2 weeks ago
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,787Updated this week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,300Updated last year
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,923Updated last month
• chipsalliance / rocket-chip
  Rocket Chip Generator
  ☆3,471Updated 3 weeks ago
• openhwgroup / cva6
  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  ☆2,513Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,135Updated 2 weeks ago
• FPGAwars / apio
  Open source ecosystem for open FPGA boards
  ☆861Updated this week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,032Updated this week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,872Updated this week