Alternatives and similar repositories for icestorm:

Users that are interested in icestorm are comparing it to the libraries listed below

• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆67Updated 3 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆82Updated last year
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆31Updated 4 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆134Updated last month
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated 4 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated this week
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆54Updated last year
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆86Updated 6 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated this week
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆83Updated 6 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆59Updated 2 months ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆76Updated 3 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆88Updated 5 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆134Updated 3 years ago