f4pga / icestorm

Related projects ⓘ

Alternatives and complementary repositories for icestorm

• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆84Updated 5 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆115Updated last month
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆35Updated last year
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆63Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆51Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆22Updated 4 years ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆29Updated 4 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• olofk / observer
  ☆40Updated 4 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆111Updated 3 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆80Updated 11 months ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• olofk / vidbo
  Virtual Development Board
  ☆58Updated 2 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 5 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆42Updated this week
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆36Updated 6 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆52Updated 2 years ago
• andylithia / Project-Yatsuhashi-Chip1
  ☆39Updated last year
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆60Updated 3 weeks ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆36Updated last year
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆47Updated 10 months ago