Alternatives and similar repositories for fpga-tool-perf

Users that are interested in fpga-tool-perf are comparing it to the libraries listed below

• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆136Updated last month
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 3 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆99Updated last month
• chipsalliance / uvm-verilator
  ☆92Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆92Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆63Updated 11 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 2 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆117Updated 7 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 8 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆56Updated 3 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated last week
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆44Updated 7 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆179Updated 3 weeks ago
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆103Updated this week
• pieter3d / simview
  ☆78Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆145Updated 11 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆90Updated 2 months ago
• chipsalliance / AIB-specification
  Home of the Advanced Interface Bus (AIB) specification.
  ☆52Updated 2 years ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆97Updated this week
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated last week
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆91Updated 2 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆190Updated 2 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆145Updated 6 months ago