Alternatives and similar repositories for fpga-tool-perf

Users that are interested in fpga-tool-perf are comparing it to the libraries listed below

• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆84Updated last year
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆119Updated 2 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated 11 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 4 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 6 months ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆102Updated 8 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 3 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆87Updated last month
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆208Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 2 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆85Updated 9 months ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 9 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆74Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆66Updated 2 weeks ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆165Updated 2 weeks ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆116Updated last year
• pulp-platform / cheshire-ihp130-o
  ☆53Updated 6 months ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆112Updated 2 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆65Updated 5 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆111Updated 4 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆130Updated 2 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 2 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated 11 months ago
• efabless / mpw_precheck
  ☆43Updated 7 months ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago