Alternatives and similar repositories for fpga-tool-perf:

Users that are interested in fpga-tool-perf are comparing it to the libraries listed below

• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 11 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 11 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last month
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆133Updated 3 weeks ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 2 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆89Updated 3 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆95Updated last month
• chipsalliance / uvm-verilator
  ☆92Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆113Updated last year
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆78Updated 4 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 4 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆113Updated 6 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆61Updated 11 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 7 months ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆44Updated 7 months ago
• pieter3d / simview
  ☆77Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆51Updated 3 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated this week
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆153Updated last week
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated 2 weeks ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆58Updated 3 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated last month
• idea-fasoc / fasoc
  ☆54Updated last year
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆113Updated 6 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆176Updated last week
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆41Updated 4 months ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆64Updated 4 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆57Updated 3 months ago