chipsalliance / fpga-tool-perf

Related projects ⓘ

Alternatives and complementary repositories for fpga-tool-perf

• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆81Updated 6 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆115Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆95Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆51Updated last month
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆100Updated last month
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆133Updated 5 months ago
• FPGA-Research-Manchester / FABulous
  Fabric generator and CAD tools
  ☆148Updated last week
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆65Updated this week
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆77Updated 2 weeks ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆202Updated last week
• chipsalliance / uvm-verilator
  ☆75Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆129Updated 2 weeks ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• pieter3d / simview
  ☆76Updated 8 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆78Updated 3 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆169Updated this week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆136Updated 2 weeks ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆98Updated 3 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆135Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆52Updated 2 years ago
• efabless / chipignite-resources
  ☆76Updated 2 years ago
• efabless / mpw_precheck
  ☆36Updated last month
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆108Updated 3 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 5 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆63Updated 7 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆110Updated 4 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆64Updated 2 months ago