chipsalliance / fpga-tool-perfLinks
FPGA tool performance profiling
☆102Updated last year
Alternatives and similar repositories for fpga-tool-perf
Users that are interested in fpga-tool-perf are comparing it to the libraries listed below
Sorting:
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated last year
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆102Updated 7 months ago
- A SystemVerilog source file pickler.☆60Updated 10 months ago
- ☆56Updated 3 years ago
- FuseSoC standard core library☆147Updated 3 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated last year
- pulp_soc is the core building component of PULP based SoCs☆80Updated 6 months ago
- Open-source FPGA research and prototyping framework.☆208Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- The multi-core cluster of a PULP system.☆108Updated this week
- Mutation Cover with Yosys (MCY)☆87Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆116Updated 11 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆108Updated 4 years ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆110Updated last month
- Generic Register Interface (contains various adapters)☆128Updated last month
- Framework Open EDA Gui☆68Updated 9 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated 11 months ago
- Fabric generator and CAD tools.☆196Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 7 months ago
- ☆55Updated last year
- Raptor end-to-end FPGA Compiler and GUI☆84Updated 9 months ago
- ☆79Updated this week
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆124Updated 3 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- An automatic clock gating utility☆50Updated 5 months ago
- ☆52Updated 5 months ago