minerva-cpu / minerva
A 32-bit RISC-V soft processor
☆301Updated 7 months ago
Related projects: ⓘ
- Small footprint and configurable DRAM core☆371Updated 2 weeks ago
- Multi-platform nightly builds of open source FPGA tools☆288Updated 2 years ago
- A simple RISC-V processor for use in FPGA designs.☆258Updated last month
- Example designs showing different ways to use F4PGA toolchains.☆263Updated 5 months ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆270Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆147Updated 5 months ago
- VHDL synthesis (based on ghdl)☆301Updated 2 months ago
- The original high performance and small footprint system-on-chip based on Migen™☆305Updated 4 months ago
- Basic RISC-V CPU implementation in VHDL.☆158Updated 4 years ago
- Documenting the Lattice ECP5 bit-stream format.☆396Updated 7 months ago
- A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.☆203Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆280Updated 3 weeks ago
- A utility for Composing FPGA designs from Peripherals☆167Updated 8 months ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆223Updated this week
- An abstraction library for interfacing EDA tools☆622Updated 3 weeks ago
- RISC-V CPU Core☆280Updated 3 months ago
- Experimental flows using nextpnr for Xilinx devices☆206Updated 7 months ago
- An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!☆214Updated 2 years ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆298Updated last year
- FOSS Flow For FPGA☆350Updated last month
- RISC-V Debug Support for our PULP RISC-V Cores☆213Updated last month
- Bus bridges and other odds and ends☆470Updated 8 months ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆387Updated this week
- CORE-V Family of RISC-V Cores☆199Updated 7 months ago
- VHDL library 4 FPGAs☆167Updated this week
- Linux on LiteX-VexRiscv☆566Updated 2 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆305Updated 2 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆208Updated last month
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆389Updated this week
- Small footprint and configurable PCIe core☆465Updated this week