Alternatives and similar repositories for minerva

Users that are interested in minerva are comparing it to the libraries listed below

• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆160Updated 8 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆297Updated last week
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆299Updated 4 years ago
• m-labs / misoc
  The original high performance and small footprint system-on-chip based on Migen™
  ☆339Updated 2 weeks ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆283Updated last year
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆433Updated last month
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆278Updated last year
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆171Updated 5 years ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆459Updated last week
• timvideos / litex-buildenv
  An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!
  ☆219Updated 3 years ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆248Updated last year
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆187Updated last month
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆312Updated 2 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated 11 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆353Updated last month
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆271Updated last month
• olofk / corescore
  CoreScore
  ☆169Updated 3 weeks ago
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆242Updated 6 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆318Updated last year
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆139Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆149Updated 6 months ago
• RobertBaruch / nmigen-tutorial
  A tutorial for using nmigen
  ☆312Updated 4 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• stnolting / neo430
  A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
  ☆205Updated 4 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆182Updated this week
• ZipCPU / vgasim
  A Video display simulator
  ☆174Updated 6 months ago
• emard / ulx3s
  PCB for ULX3S FPGA R&D board
  ☆417Updated 7 months ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆374Updated 2 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆332Updated 11 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆247Updated last year