Alternatives and similar repositories for minerva

Users that are interested in minerva are comparing it to the libraries listed below

• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆299Updated 3 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆279Updated last year
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆434Updated last month
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆159Updated 5 months ago
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆424Updated 3 months ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆169Updated 4 years ago
• m-labs / misoc
  The original high performance and small footprint system-on-chip based on Migen™
  ☆333Updated 2 weeks ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• timvideos / litex-buildenv
  An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!
  ☆219Updated 3 years ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆292Updated last week
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆343Updated 3 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆244Updated 10 months ago
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆309Updated 2 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆255Updated this week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆309Updated last year
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆240Updated 3 months ago
• olofk / corescore
  CoreScore
  ☆162Updated 2 weeks ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆183Updated 8 months ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆180Updated 2 weeks ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 3 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆323Updated 8 months ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆446Updated 11 months ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆114Updated 4 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 9 months ago
• ZipCPU / vgasim
  A Video display simulator
  ☆171Updated 3 months ago
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆327Updated 3 years ago
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆413Updated last month
• stnolting / neo430
  A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
  ☆203Updated 3 years ago