Alternatives and similar repositories for minerva:

Users that are interested in minerva are comparing it to the libraries listed below

• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆152Updated 9 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆266Updated 5 months ago
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆294Updated 3 years ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆388Updated 3 weeks ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆278Updated this week
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆272Updated 10 months ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆223Updated 3 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆304Updated 7 months ago
• m-labs / misoc
  The original high performance and small footprint system-on-chip based on Migen™
  ☆315Updated 2 weeks ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆317Updated last month
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 2 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆306Updated last month
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆170Updated last month
• chipsalliance / Cores-VeeR-EH2
  ☆222Updated 2 years ago
• timvideos / litex-buildenv
  An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!
  ☆215Updated 2 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆259Updated this week
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆404Updated 2 weeks ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆165Updated 4 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆238Updated 2 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆287Updated last year
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆368Updated 3 weeks ago
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆304Updated last year
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆220Updated last week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆125Updated this week
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆169Updated last week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆221Updated this week
• olofk / corescore
  CoreScore
  ☆142Updated this week
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆134Updated 2 years ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆655Updated this week
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆232Updated last month