minerva-cpu / minervaLinks
A 32-bit RISC-V soft processor
☆316Updated last week
Alternatives and similar repositories for minerva
Users that are interested in minerva are comparing it to the libraries listed below
Sorting:
- A simple RISC-V processor for use in FPGA designs.☆282Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆296Updated last week
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 8 months ago
- Multi-platform nightly builds of open source FPGA tools☆299Updated 4 years ago
- Example designs showing different ways to use F4PGA toolchains.☆276Updated last year
- Documenting the Lattice ECP5 bit-stream format.☆431Updated 3 weeks ago
- Small footprint and configurable DRAM core☆456Updated last month
- The original high performance and small footprint system-on-chip based on Migen™☆338Updated 2 weeks ago
- Basic RISC-V CPU implementation in VHDL.☆171Updated 5 years ago
- Experimental flows using nextpnr for Xilinx devices☆246Updated last year
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- CoreScore☆167Updated this week
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Small footprint and configurable Ethernet core☆270Updated last week
- A simple, basic, formally verified UART controller☆314Updated last year
- FuseSoC standard core library☆148Updated 5 months ago
- Example LED blinking project for your FPGA dev board of choice☆186Updated last month
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆242Updated 5 months ago
- VHDL synthesis (based on ghdl)☆352Updated 2 weeks ago
- An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!☆219Updated 3 years ago
- A Video display simulator☆174Updated 6 months ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆310Updated 2 years ago
- 😎 A curated list of awesome RISC-V implementations☆138Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆331Updated 11 months ago
- VHDL library 4 FPGAs☆181Updated this week
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆412Updated last week
- A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.☆205Updated 3 years ago
- FOSS Flow For FPGA☆412Updated 10 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆246Updated last year
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆328Updated 3 years ago