Place and route tool for FPGAs
☆422Jul 28, 2019Updated 7 years ago
Alternatives and similar repositories for arachne-pnr
Users that are interested in arachne-pnr are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,195Nov 2, 2026Updated last week
- Yosys Open SYnthesis Suite☆4,887Updated this week
- nextpnr portable FPGA place and route tool☆1,793Updated this week
- public domain tools for FPGAs☆332Feb 7, 2017Updated 9 years ago
- Open FPGA tools☆259Mar 30, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆64Oct 10, 2023Updated 3 years ago
- ☆115Feb 2, 2021Updated 5 years ago
- Tools and Examples for IcoBoard☆80Jul 13, 2021Updated 5 years ago
- A VHDL frontend for Yosys☆105Feb 27, 2017Updated 9 years ago
- Yosys Plugins☆23Jul 16, 2019Updated 7 years ago
- Documenting the Xilinx 7-series bit-stream format.☆931Jun 5, 2025Updated last year
- Documenting the Lattice ECP5 bit-stream format.☆478Oct 31, 2026Updated last week
- Visual editor for open FPGA boards☆1,951Updated this week
- Python script for programming the iCEBlink40 development board under linux☆34Jun 29, 2018Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Open source design files for the TinyFPGA B-Series boards.☆201Nov 10, 2021Updated 5 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆17May 23, 2020Updated 6 years ago
- The CAT Board is a Raspberry Pi HAT with a Lattice iCE40HX FPGA.☆64Feb 27, 2024Updated 2 years ago
- A Python toolbox for building complex digital hardware☆1,329Jan 5, 2026Updated 10 months ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,282Updated this week
- GUI for SymbiYosys☆19Aug 4, 2026Updated 3 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,400Sep 7, 2026Updated 2 months ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆569Updated this week
- Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site☆13Jun 25, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆321Updated this week
- Icestorm, Arachne-pnr and Yosys pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS☆40May 9, 2022Updated 4 years ago
- Benchmarks for Yosys development☆25Feb 17, 2020Updated 6 years ago
- Swapforth is a cross-platform ANS Forth☆306Dec 26, 2023Updated 2 years ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆313May 25, 2023Updated 3 years ago
- Small and low cost FPGA educational and development board☆678May 24, 2026Updated 5 months ago
- Exploration of alternative hardware description languages☆28Mar 9, 2018Updated 8 years ago
- verilog tutorials for iCE40HX8K Breakout Board☆23Mar 2, 2016Updated 10 years ago
- Public examples of ICE40 HX8K examples using Icestorm☆116Apr 24, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- The original high performance and small footprint system-on-chip based on Migen™☆341Jan 5, 2026Updated 10 months ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 7 years ago
- Collection of test cases for Yosys☆18Jan 4, 2022Updated 4 years ago
- A Verilog Synthesis Regression Test☆40Jan 19, 2026Updated 9 months ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆33Jan 22, 2022Updated 4 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆127Jul 7, 2016Updated 10 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆91Feb 9, 2022Updated 4 years ago
Are these results useful?