olofk / fusesocLinks
Package manager and build abstraction tool for FPGA/ASIC development
☆1,325Updated this week
Alternatives and similar repositories for fusesoc
Users that are interested in fusesoc are comparing it to the libraries listed below
Sorting:
- VUnit is a unit testing framework for VHDL/SystemVerilog☆784Updated last week
- An abstraction library for interfacing EDA tools☆707Updated 3 weeks ago
- cocotb: Python-based chip (RTL) verification☆2,058Updated last week
- Documenting the Xilinx 7-series bit-stream format.☆818Updated 2 months ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆585Updated 3 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,609Updated 2 weeks ago
- Verilog library for ASIC and FPGA designers☆1,330Updated last year
- SERV - The SErial RISC-V CPU☆1,630Updated 2 months ago
- VeeR EH1 core☆889Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,109Updated 2 months ago
- nextpnr portable FPGA place and route tool☆1,494Updated this week
- A small, light weight, RISC CPU soft core☆1,449Updated 2 weeks ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆674Updated last month
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,132Updated this week
- SystemVerilog to Verilog conversion☆659Updated 2 months ago
- Bus bridges and other odds and ends☆582Updated 4 months ago
- An Open-source FPGA IP Generator☆981Updated last week
- A Python toolbox for building complex digital hardware☆1,301Updated 2 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,353Updated last week
- Linux on LiteX-VexRiscv☆655Updated last month
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆402Updated this week
- An open-source static random access memory (SRAM) compiler.☆936Updated last month
- RISC-V Formal Verification Framework☆607Updated 3 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆598Updated last week
- A Linux-capable RISC-V multicore for and by the world☆721Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆926Updated 9 months ago
- Common SystemVerilog components☆649Updated this week
- Multi-platform nightly builds of open source digital design and verification tools☆1,137Updated this week
- Modular hardware build system☆1,063Updated this week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆634Updated 3 weeks ago