Alternatives and similar repositories for fusesoc

Users that are interested in fusesoc are comparing it to the libraries listed below

• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆784Updated 2 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆705Updated last week
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆584Updated 4 years ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,050Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆816Updated last month
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,320Updated last year
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,479Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,615Updated last month
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,595Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆653Updated last month
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆885Updated 2 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,098Updated 2 months ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆928Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆719Updated 3 months ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆402Updated 2 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆672Updated 2 weeks ago
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,295Updated last month
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆576Updated 3 months ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆964Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,119Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,438Updated 5 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆593Updated last week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆925Updated 8 months ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆654Updated last month
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,339Updated last week
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆628Updated this week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,058Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆637Updated last week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,124Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆463Updated this week