PrincetonUniversity / prgaLinks
Open-source FPGA research and prototyping framework.
☆207Updated 11 months ago
Alternatives and similar repositories for prga
Users that are interested in prga are comparing it to the libraries listed below
Sorting:
- Fabric generator and CAD tools.☆190Updated this week
- Advanced Interface Bus (AIB) die-to-die hardware open source☆138Updated 9 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- FPGA tool performance profiling☆102Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 2 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- FuseSoC standard core library☆144Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆151Updated last week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆106Updated 2 months ago
- SystemVerilog frontend for Yosys☆135Updated last week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆144Updated last month
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆114Updated 3 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- SystemVerilog synthesis tool☆201Updated 4 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆139Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆85Updated last week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- A SystemVerilog source file pickler.☆59Updated 8 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆89Updated 6 years ago
- WAL enables programmable waveform analysis.☆155Updated last month
- Provides dot visualizations of chisel/firrtl circuits☆119Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆111Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆168Updated 7 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆262Updated 3 weeks ago
- ☆56Updated 3 years ago
- ☆66Updated 2 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆160Updated last month
- Chisel components for FPGA projects☆124Updated last year