Alternatives and similar repositories for prga

Users that are interested in prga are comparing it to the libraries listed below

• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆146Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆184Updated 9 months ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆105Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆217Updated this week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆164Updated 3 months ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆147Updated 2 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated 2 months ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆92Updated 6 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆227Updated 11 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆91Updated last week
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆220Updated last month
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆119Updated 4 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆186Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆80Updated last year
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆153Updated last month
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆310Updated this week
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆174Updated this week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated last month
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆119Updated 8 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆170Updated 5 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆109Updated 4 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 7 months ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆123Updated 2 weeks ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆136Updated this week
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆88Updated 4 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆122Updated 4 years ago