Alternatives and similar repositories for StdCellLib

Users that are interested in StdCellLib are comparing it to the libraries listed below

• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆70Updated 3 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆144Updated last year
• rubund / graywolf
  ☆112Updated 4 years ago
• libresilicon / qtflow
  Free open source EDA tools
  ☆66Updated 5 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆114Updated 3 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆115Updated 4 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated this week
• libresilicon / process
  ☆91Updated 6 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• s-holst / GDS2WebGL
  Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.
  ☆57Updated 5 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆124Updated 9 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆34Updated 3 years ago
• wulffern / ciccreator
  Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…
  ☆34Updated 2 months ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 10 months ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 9 months ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 3 years ago
• gatecat / TrellisBoard
  Ultimate ECP5 development board
  ☆111Updated 6 years ago
• enjoy-digital / litescope
  Small footprint and configurable embedded FPGA logic analyzer
  ☆185Updated 3 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆117Updated last year
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆69Updated last month
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆46Updated 2 months ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• olofk / corescore
  CoreScore
  ☆162Updated 2 weeks ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆81Updated 3 years ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆98Updated 2 years ago
• efabless / mpw_precheck
  ☆42Updated 6 months ago