Alternatives and similar repositories for StdCellLib

Users that are interested in StdCellLib are comparing it to the libraries listed below

• rubund / graywolf
  ☆113Updated 4 years ago
• libresilicon / qtflow
  Free open source EDA tools
  ☆66Updated 5 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆70Updated 3 years ago
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆143Updated last year
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆34Updated 3 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆124Updated 9 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 3 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 9 months ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆65Updated last week
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• gatecat / TrellisBoard
  Ultimate ECP5 development board
  ☆111Updated 6 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆79Updated 3 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆114Updated 3 years ago
• wulffern / ciccreator
  Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…
  ☆34Updated 3 weeks ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆68Updated this week
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆56Updated 2 years ago
• dovebutch / tlv-comp
  ☆27Updated 5 months ago
• pieter3d / simview
  ☆79Updated last year
• SymbiFlow / yosys
  SymbiFlow WIP changes for Yosys Open SYnthesis Suite
  ☆39Updated last year
• libresilicon / process
  ☆91Updated 5 years ago
• olofk / corescore
  CoreScore
  ☆157Updated 5 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆59Updated last month
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆109Updated 2 years ago
• enjoy-digital / litescope
  Small footprint and configurable embedded FPGA logic analyzer
  ☆184Updated last month