Alternatives and similar repositories for python-fpga-interchange

Users that are interested in python-fpga-interchange are comparing it to the libraries listed below

• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆78Updated 4 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 11 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆71Updated 10 months ago
• efabless / sky130_sram_macros_old
  ☆37Updated 3 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆30Updated 4 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆53Updated this week
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆89Updated 6 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆57Updated this week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 5 years ago
• pulp-platform / svase
  ☆32Updated 6 months ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆40Updated 2 weeks ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 2 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 weeks ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated this week
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated 2 weeks ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 9 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆29Updated last year