lnis-uofu / SOFALinks
SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
☆142Updated 2 years ago
Alternatives and similar repositories for SOFA
Users that are interested in SOFA are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆147Updated 3 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆156Updated 2 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆116Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆109Updated 4 years ago
- ☆83Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated last year
- Fabric generator and CAD tools.☆197Updated last week
- ☆116Updated 2 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆94Updated last week
- ☆136Updated 9 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆124Updated 4 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- VHDL library 4 FPGAs☆181Updated this week
- Building and deploying container images for open source electronic design automation (EDA)☆116Updated 11 months ago
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆72Updated last month
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 6 months ago
- Python script to transform a VCD file to wavedrom format☆80Updated 3 years ago
- A curated list of awesome resources for HDL design and verification☆158Updated last week
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆216Updated 2 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆137Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 8 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated last month
- SystemVerilog synthesis tool☆209Updated 6 months ago
- Open-source FPGA research and prototyping framework.☆208Updated last year
- Arduino compatible Risc-V Based SOC☆156Updated last year