lnis-uofu / SOFA
SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
☆137Updated 2 years ago
Alternatives and similar repositories for SOFA:
Users that are interested in SOFA are comparing it to the libraries listed below
- FuseSoC standard core library☆130Updated 2 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 10 months ago
- Mathematical Functions in Verilog☆91Updated 4 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆134Updated 3 years ago
- ☆110Updated last year
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆64Updated last month
- Fabric generator and CAD tools☆163Updated last month
- A curated list of awesome resources for HDL design and verification☆146Updated this week
- ☆79Updated 2 years ago
- SoC based on VexRiscv and ICE40 UP5K☆155Updated 2 weeks ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆101Updated 3 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆67Updated this week
- Control and Status Register map generator for HDL projects☆114Updated last month
- SystemVerilog frontend for Yosys☆81Updated 2 weeks ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆110Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆164Updated 4 months ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆61Updated last week
- SpinalHDL Hardware Math Library☆85Updated 8 months ago
- A utility for Composing FPGA designs from Peripherals☆175Updated 3 months ago
- SystemVerilog synthesis tool☆183Updated 3 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆134Updated 2 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆63Updated 3 months ago
- ☆130Updated 3 months ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆56Updated 2 years ago
- Basic RISC-V Test SoC☆119Updated 5 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆78Updated this week