SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
☆147Mar 17, 2023Updated 2 years ago
Alternatives and similar repositories for SOFA
Users that are interested in SOFA are comparing it to the libraries listed below
Sorting:
- An Open-source FPGA IP Generator☆1,056Feb 28, 2026Updated last week
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆218Feb 23, 2026Updated last week
- Open-source FPGA research and prototyping framework.☆210Aug 8, 2024Updated last year
- Analog and power building blocks for sky130 pdk☆22Mar 3, 2021Updated 5 years ago
- ☆87Nov 7, 2022Updated 3 years ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆397Updated this week
- An open source PDK using TIGFET 10nm devices.☆56Dec 19, 2022Updated 3 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,724Sep 15, 2025Updated 5 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆92Jul 3, 2019Updated 6 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated 7 months ago
- Prefix tree adder space exploration library☆56Jan 27, 2026Updated last month
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆73Oct 4, 2021Updated 4 years ago
- IDEA project source files☆111Oct 15, 2025Updated 4 months ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆284Dec 8, 2025Updated 2 months ago
- ☆38Jul 11, 2022Updated 3 years ago
- ☆19Oct 28, 2024Updated last year
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- An open-source static random access memory (SRAM) compiler.☆1,016Jan 16, 2026Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Nov 10, 2025Updated 3 months ago
- LibreSilicon's Standard Cell Library Generator☆22Oct 30, 2025Updated 4 months ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Dec 25, 2025Updated 2 months ago
- ☆44Jan 26, 2020Updated 6 years ago
- Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP☆40Aug 16, 2021Updated 4 years ago
- ☆72Aug 19, 2024Updated last year
- FPGA tool performance profiling☆105Feb 24, 2024Updated 2 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆450Updated this week
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆129Feb 24, 2026Updated last week
- My pergola FPGA projects☆30Jun 23, 2021Updated 4 years ago
- A Linux-capable RISC-V multicore for and by the world☆771Feb 9, 2026Updated 3 weeks ago
- SystemVerilog to Verilog conversion☆706Nov 24, 2025Updated 3 months ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆19Nov 29, 2020Updated 5 years ago
- SKY130 ReRAM and examples (SkyWater Provided)☆44Apr 20, 2022Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83May 14, 2024Updated last year
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆268Mar 26, 2022Updated 3 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆24May 13, 2023Updated 2 years ago