lnis-uofu / SOFALinks
SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
☆144Updated 2 years ago
Alternatives and similar repositories for SOFA
Users that are interested in SOFA are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆148Updated 5 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆119Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last week
- ☆84Updated 3 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆117Updated 4 years ago
- Fabric generator and CAD tools.☆206Updated this week
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆125Updated 6 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆74Updated 3 months ago
- ☆119Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 3 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆117Updated 4 years ago
- ☆137Updated 11 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆123Updated 4 months ago
- ☆43Updated 3 years ago
- Bitstream relocation and manipulation tool.☆49Updated 2 years ago
- SpinalHDL Hardware Math Library☆93Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 10 months ago
- Building and deploying container images for open source electronic design automation (EDA)☆115Updated last year
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated last month
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- SystemVerilog synthesis tool☆218Updated 8 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last week
- Mathematical Functions in Verilog☆95Updated 4 years ago