Alternatives and similar repositories for simulate-gate

Users that are interested in simulate-gate are comparing it to the libraries listed below

• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 5 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆32Updated 5 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 3 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 8 months ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• FPGA-Research / FABulator
  Fabric generator and CAD tools graphical frontend
  ☆17Updated 5 months ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆31Updated last month
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• pulp-platform / svase
  ☆33Updated last year
• samlittlewood / caravel_carrier
  Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
  ☆18Updated 4 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆49Updated 3 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆31Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆56Updated last year
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 3 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆32Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• efabless / caravel_user_project_analog
  ☆50Updated 11 months ago
• snishizawa / libretto
  Characterizer
  ☆30Updated last month
• space-tudelft / cacd
  Space CACD
  ☆11Updated 6 years ago
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated 11 months ago
• tclarke / sky130radio
  components and examples for creating radio ICs using the open skywater 130nm PDK
  ☆19Updated 5 years ago
• westonb / sky130-analog
  Analog and power building blocks for sky130 pdk
  ☆21Updated 4 years ago
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆12Updated 3 weeks ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• iic-jku / SKY130_SAR-ADC1
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆50Updated 9 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 8 months ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 6 months ago