Alternatives and similar repositories for simulate-gate

Users that are interested in simulate-gate are comparing it to the libraries listed below

• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆32Updated 5 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆20Updated 4 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 6 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆52Updated 9 months ago
• FPGA-Research / FABulator
  Fabric generator and CAD tools graphical frontend
  ☆17Updated 6 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆37Updated 3 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆31Updated 2 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆34Updated 2 months ago
• iic-jku / SKY130_SAR-ADC1
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆51Updated 10 months ago
• westonb / sky130-analog
  Analog and power building blocks for sky130 pdk
  ☆22Updated 4 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆56Updated 3 years ago
• tclarke / sky130radio
  components and examples for creating radio ICs using the open skywater 130nm PDK
  ☆19Updated 5 years ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆56Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• pulp-platform / svase
  ☆33Updated last year
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆13Updated this week
• pulp-platform / pulp-ethernet
  ☆14Updated 10 months ago
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆52Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• snishizawa / libretto
  Characterizer
  ☆31Updated 2 months ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 10 months ago
• growly / bfg
  An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics
  ☆14Updated this week
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆33Updated last month
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆41Updated 2 months ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆22Updated 3 years ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆29Updated last year
• dovebutch / tlv-comp
  ☆27Updated 11 months ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆24Updated 4 years ago