mattvenn / simulate-gate
Project 1.1 Simulate a Skywater 130nm standard cell using ngspice
☆14Updated last year
Alternatives and similar repositories for simulate-gate
Users that are interested in simulate-gate are comparing it to the libraries listed below
Sorting:
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- LunaPnR is a place and router for integrated circuits☆46Updated 5 months ago
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- An automatic clock gating utility☆47Updated last month
- ☆36Updated 2 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- ☆10Updated last year
- ☆46Updated 3 months ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 3 years ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆19Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- AXI Formal Verification IP☆20Updated 4 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- Parasitic capacitance analysis of foundry metal stackups☆12Updated 2 weeks ago
- ☆35Updated 6 months ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆40Updated 2 months ago
- Cross EDA Abstraction and Automation☆38Updated last week
- ☆31Updated 4 months ago
- Characterizer☆22Updated last week
- ☆20Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- ☆22Updated last week
- Fabric generator and CAD tools graphical frontend☆12Updated last year