mattvenn / simulate-gateLinks
Project 1.1 Simulate a Skywater 130nm standard cell using ngspice
☆14Updated 4 months ago
Alternatives and similar repositories for simulate-gate
Users that are interested in simulate-gate are comparing it to the libraries listed below
Sorting:
- LunaPnR is a place and router for integrated circuits☆47Updated 4 months ago
- FPGA250 aboard the eFabless Caravel☆31Updated 4 years ago
- An automatic clock gating utility☆51Updated 7 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Fabric generator and CAD tools graphical frontend☆17Updated 3 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Example of how to use UVM with Verilator☆27Updated last month
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆48Updated 3 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated last week
- USB virtual model in C++ for Verilog☆32Updated last year
- Virtual development board for HDL design☆42Updated 2 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 4 years ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 2 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- Space CACD☆11Updated 6 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆39Updated last week
- ☆38Updated 3 years ago
- ☆14Updated 8 months ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆44Updated last week
- SystemVerilog Linter based on pyslang☆31Updated 6 months ago
- PicoRV☆43Updated 5 years ago
- Characterizer☆30Updated last week
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆10Updated 6 months ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆119Updated 2 years ago