mattvenn / simulate-gateLinks
Project 1.1 Simulate a Skywater 130nm standard cell using ngspice
☆14Updated 3 weeks ago
Alternatives and similar repositories for simulate-gate
Users that are interested in simulate-gate are comparing it to the libraries listed below
Sorting:
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- An automatic clock gating utility☆49Updated 2 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 7 months ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 3 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- A current mode buck converter on the SKY130 PDK☆27Updated 4 years ago
- ☆47Updated 4 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆43Updated 3 weeks ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- ☆37Updated 2 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 5 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- Cross EDA Abstraction and Automation☆39Updated this week
- A reconfigurable logic circuit made of identical rotatable tiles.☆22Updated 3 years ago
- AXI Formal Verification IP☆20Updated 4 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆19Updated 4 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆48Updated 2 years ago
- ☆11Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆32Updated last month
- ☆32Updated 5 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Skywater 130nm Klayout Device Generators PDK☆31Updated 11 months ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago