hdl / conda-edaLinks
Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
☆101Updated 6 months ago
Alternatives and similar repositories for conda-eda
Users that are interested in conda-eda are comparing it to the libraries listed below
Sorting:
- FPGA tool performance profiling☆102Updated last year
- Hardware Description Library☆81Updated 3 months ago
- ☆55Updated last year
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆68Updated this week
- BAG framework☆41Updated last year
- Tools for working with circuits as graphs in python☆122Updated last year
- Primitives for GF180MCU provided by GlobalFoundries.☆51Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated 10 months ago
- ☆92Updated 6 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆121Updated 2 months ago
- ☆42Updated 5 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆44Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 8 months ago
- ☆81Updated 2 years ago
- Automatic generation of real number models from analog circuits☆42Updated last year
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- Coriolis VLSI EDA Tool (LIP6)☆69Updated last week
- A SystemVerilog source file pickler.☆59Updated 9 months ago
- Open Source PHY v2☆29Updated last year
- Library of open source Process Design Kits (PDKs)☆49Updated last month
- ideas and eda software for vlsi design☆50Updated last week
- Structural Netlist API (and more) for EDA post synthesis flow development☆112Updated this week
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆64Updated last month
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆73Updated 2 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆154Updated last month
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆95Updated 5 months ago
- Interchange formats for chip design.☆31Updated 2 months ago