Alternatives and similar repositories for conda-eda:

Users that are interested in conda-eda are comparing it to the libraries listed below

• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated 11 months ago
• efabless / volare
  Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
  ☆63Updated this week
• efabless / chipignite-resources
  ☆79Updated 2 years ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆113Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆75Updated 2 weeks ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 6 months ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_pr
  Primitives for GF180MCU provided by GlobalFoundries.
  ☆48Updated last year
• idea-fasoc / fasoc
  ☆53Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 9 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 4 months ago
• efabless / mpw_precheck
  ☆36Updated 2 weeks ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆33Updated this week
• iic-jku / osic-multitool
  JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
  ☆56Updated 3 months ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆60Updated 2 weeks ago
• clin99 / awesome-eda
  ☆91Updated 5 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆62Updated last week
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆42Updated 2 weeks ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆74Updated this week
• ncsu-eda / FreePDK3
  ☆132Updated 3 years ago
• google / bigspicy
  ☆39Updated last year
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆56Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆141Updated 8 months ago
• efabless / foss-asic-tools
  FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…
  ☆79Updated 6 months ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆37Updated 10 months ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated 4 months ago
• aolofsson / POSH
  ☆40Updated 5 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆49Updated last week
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆73Updated 2 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆42Updated last month