chipsalliance / Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
☆380Updated last month
Alternatives and similar repositories for Surelog:
Users that are interested in Surelog are comparing it to the libraries listed below
- Test suite designed to check compliance with the SystemVerilog standard.☆306Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆206Updated 2 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆542Updated this week
- Common SystemVerilog components☆560Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆585Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆451Updated 3 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆285Updated 4 months ago
- SystemVerilog synthesis tool☆177Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆419Updated this week
- SystemRDL 2.0 language compiler front-end☆242Updated 3 weeks ago
- Bus bridges and other odds and ends☆511Updated last week
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆197Updated last week
- UVM 1.2 port to Python☆247Updated 10 months ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆274Updated 5 years ago
- The UVM written in Python☆398Updated 2 weeks ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆421Updated last week
- An abstraction library for interfacing EDA tools☆655Updated this week
- SystemVerilog compiler and language services☆663Updated this week
- SystemVerilog linter☆331Updated 2 weeks ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆506Updated last year
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆259Updated 3 weeks ago
- ☆194Updated last week
- VeeR EL2 Core☆259Updated this week
- Code used in☆177Updated 7 years ago
- Build Customized FPGA Implementations for Vivado☆301Updated 2 weeks ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆196Updated 3 months ago
- lowRISC Style Guides☆384Updated 4 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆264Updated this week
- Verilog Configurable Cache☆170Updated last month
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆306Updated last week