chipsalliance / Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
☆353Updated this week
Related projects: ⓘ
- Test suite designed to check compliance with the SystemVerilog standard.☆284Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆191Updated last month
- Common SystemVerilog components☆494Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆498Updated 2 weeks ago
- SystemVerilog to Verilog conversion☆535Updated 2 weeks ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆281Updated 2 weeks ago
- SystemVerilog compiler and language services☆584Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆389Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆394Updated 9 months ago
- The UVM written in Python☆358Updated last month
- SystemRDL 2.0 language compiler front-end☆226Updated 2 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆418Updated last month
- An abstraction library for interfacing EDA tools☆622Updated 3 weeks ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆266Updated 4 years ago
- Bus bridges and other odds and ends☆470Updated 8 months ago
- lowRISC Style Guides☆357Updated this week
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆480Updated last year
- Qflow full end-to-end digital synthesis flow for ASIC designs☆184Updated 4 months ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆243Updated last week
- Code used in☆168Updated 7 years ago
- UVM 1.2 port to Python☆234Updated 6 months ago
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆192Updated this week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆191Updated last year
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆253Updated this week
- A dependency management tool for hardware projects.☆230Updated 3 weeks ago
- A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.☆128Updated 5 years ago
- Verilog Configurable Cache☆165Updated 3 weeks ago
- FOSS Flow For FPGA☆350Updated last month
- VeeR EL2 Core☆243Updated this week
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆221Updated 2 weeks ago