chipsalliance / SurelogLinks
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
☆434Updated 4 months ago
Alternatives and similar repositories for Surelog
Users that are interested in Surelog are comparing it to the libraries listed below
Sorting:
- Test suite designed to check compliance with the SystemVerilog standard.☆354Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆242Updated 4 months ago
- SystemRDL 2.0 language compiler front-end☆269Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆632Updated 3 weeks ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆312Updated 6 months ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆485Updated last week
- SystemVerilog to Verilog conversion☆693Updated last month
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆461Updated 2 months ago
- SystemVerilog synthesis tool☆223Updated 10 months ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆284Updated 6 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆309Updated 3 months ago
- Common SystemVerilog components☆694Updated 3 weeks ago
- An abstraction library for interfacing EDA tools☆737Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆557Updated 2 months ago
- Code generation tool for control and status registers☆439Updated last week
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆243Updated this week
- The UVM written in Python☆491Updated 2 weeks ago
- Bus bridges and other odds and ends☆618Updated 9 months ago
- UVM 1.2 port to Python☆257Updated 11 months ago
- Build Customized FPGA Implementations for Vivado☆352Updated this week
- A dependency management tool for hardware projects.☆341Updated this week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆223Updated last year
- SystemVerilog compiler and language services☆915Updated last week
- lowRISC Style Guides☆474Updated 2 months ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆299Updated last week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆299Updated this week