SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
☆467Jul 20, 2026Updated this week
Alternatives and similar repositories for Surelog
Users that are interested in Surelog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆260Updated this week
- SystemVerilog compiler and language services☆1,089Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆380Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,894Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆478Jun 10, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆30Oct 2, 2023Updated 2 years ago
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- SystemVerilog to Verilog conversion☆741Mar 28, 2026Updated 3 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆330Jun 30, 2025Updated last year
- An abstraction library for interfacing EDA tools☆781Jul 2, 2026Updated 2 weeks ago
- SystemVerilog linter☆388Nov 6, 2025Updated 8 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆26Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆675Jul 7, 2026Updated 2 weeks ago
- cocotb: Python-based chip (RTL) verification☆2,449Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Yosys Open SYnthesis Suite☆4,613Updated this week
- Plugins for Yosys developed as part of the F4PGA project.☆85May 14, 2024Updated 2 years ago
- Code generation tool for control and status registers☆462Updated this week
- Mutation Cover with Yosys (MCY)☆96Jul 9, 2026Updated last week
- UVM 1.2 port to Python☆261Feb 9, 2025Updated last year
- SystemVerilog design elaborator into word-level netlist form☆238Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,756Updated this week
- A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.☆135Jul 17, 2019Updated 7 years ago
- A Linux-capable RISC-V multicore for and by the world☆823Jul 13, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Python packages providing a library for Verification Stimulus and Coverage☆147Jul 5, 2026Updated 2 weeks ago
- Python bindings for slang, a library for compiling SystemVerilog☆67Jan 18, 2025Updated last year
- Modular hardware build system☆1,188Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆533Updated this week
- ☆99May 20, 2026Updated 2 months ago
- Running Python code in SystemVerilog☆73May 8, 2026Updated 2 months ago
- SystemVerilog language server☆583Updated this week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆798Jun 15, 2024Updated 2 years ago
- The UVM written in Python☆560Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An Open-source FPGA IP Generator☆1,126Updated this week
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated last year
- XLS: Accelerated HW Synthesis☆1,514Updated this week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆311Jun 19, 2026Updated last month
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆166Jul 8, 2026Updated last week
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Jan 30, 2025Updated last year
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,250Updated this week