chipsalliance / Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
☆381Updated 2 months ago
Alternatives and similar repositories for Surelog:
Users that are interested in Surelog are comparing it to the libraries listed below
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆208Updated 3 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆306Updated this week
- Common SystemVerilog components☆570Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆424Updated last week
- SystemVerilog to Verilog conversion☆588Updated 2 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆454Updated this week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆288Updated 5 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆547Updated this week
- UVM 1.2 port to Python☆248Updated last week
- SystemRDL 2.0 language compiler front-end☆244Updated last month
- The UVM written in Python☆400Updated last month
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆425Updated this week
- SystemVerilog synthesis tool☆177Updated this week
- lowRISC Style Guides☆388Updated 5 months ago
- SystemVerilog compiler and language services☆675Updated this week
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆275Updated 5 years ago
- An abstraction library for interfacing EDA tools☆662Updated this week
- SystemVerilog linter☆334Updated last month
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆196Updated 3 months ago
- Build Customized FPGA Implementations for Vivado☆302Updated this week
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆280Updated this week
- magma circuits☆255Updated 3 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆265Updated this week
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆200Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆489Updated this week
- Fabric generator and CAD tools☆159Updated this week
- SystemVerilog support in VS Code☆133Updated last month
- Bus bridges and other odds and ends☆518Updated last week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆264Updated this week
- A dependency management tool for hardware projects.☆280Updated 2 weeks ago