Alternatives and similar repositories for litehyperbus

Users that are interested in litehyperbus are comparing it to the libraries listed below

• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆31Updated 5 years ago
• xobs / coriolis
  An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.
  ☆11Updated 7 years ago
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆21Updated 4 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 5 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 7 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆39Updated last year
• enjoy-digital / litesata_axiom
  ☆13Updated 4 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆22Updated 6 years ago
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 7 years ago
• m-labs / microscope
  Finding the bacteria in rotting FPGA designs.
  ☆14Updated 4 years ago
• xobs / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆12Updated 6 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆62Updated last week
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆23Updated 3 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆67Updated 3 weeks ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆50Updated 8 months ago
• mcci-catena / catena-riscv32-fpga
  RISC-V 32-bit core for MCCI Catena 4710
  ☆10Updated 6 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆45Updated this week
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆54Updated 2 weeks ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆45Updated 4 months ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆31Updated 11 months ago
• m-labs / nmigen-stdio
  Industry standard I/O for nMigen
  ☆12Updated 5 years ago
• litex-hub / wishbone-utils
  Utilities for working with a Wishbone bus in an embedded device
  ☆46Updated last month
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 7 years ago
• chili-chips-ba / openCologne-PCIE
  The first-ever opensource RTL stack for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With sta…
  ☆22Updated this week
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆20Updated 3 months ago
• jeanthom / gram
  DDR3 controller for nMigen (WIP)
  ☆14Updated last year