Alternatives and similar repositories for mcy

Users that are interested in mcy are comparing it to the libraries listed below

• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆52Updated 9 months ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆120Updated 8 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated 2 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 10 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆194Updated last week
• pulp-platform / svase
  ☆33Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 3 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆56Updated last week
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆105Updated last year
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆122Updated 4 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆22Updated 4 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆33Updated 2 months ago
• phanrahan / mantle
  mantle library
  ☆44Updated 3 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated last week
• pieter3d / simview
  ☆89Updated 3 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year