YosysHQ / mcy
Mutation Cover with Yosys (MCY)
☆80Updated 2 weeks ago
Alternatives and similar repositories for mcy:
Users that are interested in mcy are comparing it to the libraries listed below
- A SystemVerilog source file pickler.☆55Updated 4 months ago
- SystemVerilog frontend for Yosys☆76Updated this week
- ☆36Updated 2 years ago
- FuseSoC standard core library☆126Updated last month
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 9 months ago
- ☆54Updated 2 years ago
- Xilinx Unisim Library in Verilog☆75Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- Hardware generator debugger☆73Updated last year
- ☆31Updated last year
- FPGA tool performance profiling☆102Updated last year
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆99Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- An automatic clock gating utility☆44Updated 7 months ago
- ☆77Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆43Updated 5 months ago
- ☆31Updated last month
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 5 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 6 months ago
- RISC-V Formal Verification Framework☆128Updated last month
- A Verilog Synthesis Regression Test☆37Updated 11 months ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- WAL enables programmable waveform analysis.☆146Updated this week
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 7 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆65Updated last month
- Demo SoC for SiliconCompiler.☆56Updated last month