Alternatives and similar repositories for mcy

Users that are interested in mcy are comparing it to the libraries listed below

• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆103Updated this week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 11 months ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆83Updated 7 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆136Updated last month
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆77Updated 4 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated 3 weeks ago
• pieter3d / simview
  ☆78Updated last year
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆59Updated 2 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated 4 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆98Updated last month
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated last week
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated last year
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 3 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆93Updated 7 months ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 4 years ago
• pulp-platform / svase
  ☆31Updated 4 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆103Updated 5 months ago