Alternatives and similar repositories for mcy

Users that are interested in mcy are comparing it to the libraries listed below

• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆78Updated 4 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 2 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• efabless / sky130_sram_macros_old
  ☆37Updated 3 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆135Updated this week
• Kuree / hgdb
  Hardware generator debugger
  ☆74Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 8 months ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆106Updated last month
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆144Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• pieter3d / simview
  ☆79Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆59Updated last month
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆89Updated 6 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆94Updated 9 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆58Updated last week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆109Updated last month
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆44Updated last month
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 7 months ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆68Updated this week
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆79Updated 3 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆64Updated 5 years ago