Alternatives and similar repositories for mcy:

Users that are interested in mcy are comparing it to the libraries listed below

• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆81Updated 2 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 5 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 10 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆75Updated 4 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆130Updated 2 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆111Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆88Updated 2 weeks ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• pulp-platform / cheshire-ihp130-o
  ☆34Updated this week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆103Updated 4 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆40Updated last year
• pulp-platform / svase
  ☆31Updated 2 months ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆101Updated 3 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆147Updated last month
• pieter3d / simview
  ☆77Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆183Updated 3 weeks ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated last year
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆131Updated 3 weeks ago