YosysHQ / mcy
Mutation Cover with Yosys (MCY)
☆79Updated last week
Alternatives and similar repositories for mcy:
Users that are interested in mcy are comparing it to the libraries listed below
- 👾 Design ∪ Hardware☆73Updated 2 months ago
- ☆36Updated 2 years ago
- SystemVerilog frontend for Yosys☆69Updated last week
- FuseSoC standard core library☆125Updated this week
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 8 months ago
- A SystemVerilog source file pickler.☆54Updated 3 months ago
- Hardware generator debugger☆73Updated 11 months ago
- Announcements related to Verilator☆38Updated 4 years ago
- An automatic clock gating utility☆43Updated 6 months ago
- Yet Another RISC-V Implementation☆86Updated 4 months ago
- ☆31Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆99Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆86Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification