Mutation Cover with Yosys (MCY)
☆99Sep 9, 2026Updated last week
Alternatives and similar repositories for mcy
Users that are interested in mcy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆548Sep 9, 2026Updated last week
- Equivalence checking with Yosys☆63Updated this week
- A reconfigurable logic circuit made of identical rotatable tiles.☆25Nov 15, 2021Updated 4 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- PicoRV☆45Feb 19, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Trying to verify Verilog/VHDL designs with formal methods and tools☆44Mar 7, 2024Updated 2 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆40Jan 11, 2026Updated 8 months ago
- SystemVerilog design elaborator into word-level netlist form☆250Updated this week
- A Just-In-Time Compiler for Verilog from VMware Research☆22Dec 14, 2020Updated 5 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Sep 7, 2026Updated last week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆104Mar 29, 2024Updated 2 years ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Updated this week
- AXI Formal Verification IP☆25Apr 28, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Yosys plugin for synthesis of Bluespec code☆17Sep 8, 2021Updated 5 years ago
- Fluid Pipelines☆11May 4, 2018Updated 8 years ago
- SystemVerilog synthesis tool☆237Mar 10, 2025Updated last year
- Test suite designed to check compliance with the SystemVerilog standard.☆394Updated this week
- RISC-V Formal Verification Framework☆214Jul 15, 2026Updated 2 months ago
- SystemVerilog to Verilog conversion☆753Aug 18, 2026Updated last month
- Virtual development board for HDL design☆43Mar 31, 2023Updated 3 years ago
- A padring generator for ASICs☆26May 17, 2023Updated 3 years ago
- Multi-platform nightly builds of open source FPGA tools☆306Nov 3, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- Space CACD☆11Oct 16, 2019Updated 6 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆18Feb 3, 2026Updated 7 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆94Jul 3, 2019Updated 7 years ago
- An abstraction library for interfacing EDA tools☆795Updated this week
- Benchmarks for Yosys development☆25Feb 17, 2020Updated 6 years ago
- RISC-V RV32I CPU written in verilog