Alternatives and similar repositories for KinglerPAR:

Users that are interested in KinglerPAR are comparing it to the libraries listed below

• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆11Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆22Updated 4 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• jeanthom / gram
  DDR3 controller for nMigen (WIP)
  ☆14Updated last year
• b224hisl / rioschip
  ☆33Updated 2 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated last month
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• chipsalliance / f4pga-xc7-bram-patch
  Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.
  ☆18Updated 3 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆44Updated this week
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 6 months ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 9 months ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆31Updated 4 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆48Updated 3 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 weeks ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆21Updated 5 years ago
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 7 years ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• daveshah1 / flow-examples
  Misc open FPGA flow examples
  ☆8Updated 5 years ago