Alternatives and similar repositories for padring:

Users that are interested in padring are comparing it to the libraries listed below

• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 7 months ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆43Updated this week
• b224hisl / rioschip
  ☆33Updated 2 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆27Updated 11 months ago
• diadatp / sky130_rf_tools
  Guides and templates for using open source RF design tools with the SkyWater SKY130 process.
  ☆18Updated 4 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 4 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 11 months ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆46Updated 2 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆36Updated 3 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆20Updated 2 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 7 months ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 2 years ago
• jazvw / chip_art
  Convert an image to a GDS format for inclusion in a zerotoasic project
  ☆13Updated 2 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆42Updated 2 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆20Updated 3 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆39Updated 2 weeks ago
• clairexen / picorv
  PicoRV
  ☆44Updated 4 years ago
• efabless / caravel-lite
  ☆15Updated 3 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• pulp-platform / svase
  ☆31Updated last month
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆32Updated 2 years ago