Alternatives and similar repositories for fpu

Users that are interested in fpu are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆706Updated this week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆858Updated 11 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆632Updated 9 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆568Updated 3 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆457Updated 8 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆533Updated 11 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,487Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆641Updated 3 weeks ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆417Updated 4 months ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆614Updated 7 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆560Updated 4 years ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆699Updated 2 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆871Updated 4 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆476Updated 3 months ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆609Updated 3 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆539Updated last year
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,176Updated 4 years ago
• ucb-bar / berkeley-hardfloat
  ☆367Updated 4 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,176Updated 8 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆485Updated 2 months ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆508Updated 6 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆680Updated 11 months ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆600Updated 4 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆499Updated 2 weeks ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,952Updated 11 months ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆570Updated 3 years ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆357Updated 8 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,107Updated last year
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆759Updated this week
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆689Updated last week