dawsonjon / fpu
synthesiseable ieee 754 floating point library in verilog
☆624Updated 2 years ago
Alternatives and similar repositories for fpu:
Users that are interested in fpu are comparing it to the libraries listed below
- Verilog AXI stream components for FPGA implementation☆802Updated 2 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,267Updated this week
- Common SystemVerilog components☆608Updated 3 weeks ago
- Bus bridges and other odds and ends☆552Updated 3 weeks ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆330Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆488Updated 2 months ago
- Various HDL (Verilog) IP Cores☆779Updated 3 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆445Updated 3 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆570Updated last week
- Verilog UART☆480Updated 2 months ago
- SystemVerilog to Verilog conversion☆621Updated last month
- Verilog AXI components for FPGA implementation☆1,700Updated 2 months ago
- lowRISC Style Guides☆425Updated 7 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,063Updated 2 months ago
- Verilog SDRAM memory controller☆329Updated 7 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆572Updated 9 months ago
- AMBA bus lecture material☆432Updated 5 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆422Updated 2 weeks ago
- The UVM written in Python☆423Updated 3 weeks ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆421Updated last month
- Verilog PCI express components☆1,279Updated last year
- 32-bit Superscalar RISC-V CPU☆1,005Updated 3 years ago
- ☆322Updated 7 months ago
- A Linux-capable RISC-V multicore for and by the world☆688Updated last week
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆573Updated 7 years ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆490Updated 5 months ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆706Updated 10 months ago
- SystemVerilog compiler and language services☆737Updated this week
- Support for Rocket Chip on Zynq FPGAs☆407Updated 6 years ago
- Verilog I2C interface for FPGA implementation☆604Updated 2 months ago