synthesiseable ieee 754 floating point library in verilog
☆721Mar 13, 2023Updated 2 years ago
Alternatives and similar repositories for fpu
Users that are interested in fpu are comparing it to the libraries listed below
Sorting:
- Mathematical Functions in Verilog☆97Mar 7, 2021Updated 4 years ago
- IEEE 754 floating point unit in Verilog☆149May 20, 2016Updated 9 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆570Oct 21, 2025Updated 4 months ago
- Verilog AXI components for FPGA implementation☆1,965Feb 27, 2025Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,500Updated this week
- 32-bit Superscalar RISC-V CPU☆1,179Sep 18, 2021Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Jan 2, 2026Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆649Jan 19, 2026Updated last month
- ☆367Sep 12, 2025Updated 5 months ago
- Verilog PCI express components☆1,541Apr 26, 2024Updated last year
- ☆58Feb 18, 2019Updated 7 years ago
- Verilog library for ASIC and FPGA designers☆1,392May 8, 2024Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 7 months ago
- IC implementation of Systolic Array for TPU☆339Oct 21, 2024Updated last year
- Basic floating-point components for RISC-V processors☆67Dec 4, 2019Updated 6 years ago
- Verilog UART☆536Feb 27, 2025Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆196Updated this week
- Common SystemVerilog components☆713Updated this week
- Must-have verilog systemverilog modules☆1,934Feb 19, 2026Updated last week
- A DDR3 memory controller in Verilog for various FPGAs☆569Oct 10, 2021Updated 4 years ago
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆225Sep 14, 2023Updated 2 years ago
- Various HDL (Verilog) IP Cores☆876Jul 1, 2021Updated 4 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,817Feb 18, 2026Updated last week
- Verilog Configurable Cache☆192Feb 17, 2026Updated last week
- RTL, Cmodel, and testbench for NVDLA☆2,025Mar 2, 2022Updated 3 years ago
- Verilog AXI stream components for FPGA implementation☆862Feb 27, 2025Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆963Nov 15, 2024Updated last year
- Verilog I2C interface for FPGA implementation☆682Feb 27, 2025Updated last year
- Opensource DDR3 Controller☆418Jan 18, 2026Updated last month
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,966Jun 27, 2024Updated last year
- ☆93Updated this week
- SystemVerilog to Verilog conversion☆704Nov 24, 2025Updated 3 months ago
- AMBA bus lecture material☆512Jan 21, 2020Updated 6 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,187May 26, 2025Updated 9 months ago
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- RISC-V System on Chip Builder☆12Sep 27, 2020Updated 5 years ago
- Generic Register Interface (contains various adapters)☆136Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆258Nov 6, 2024Updated last year
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆68Aug 10, 2024Updated last year