dawsonjon / fpu
synthesiseable ieee 754 floating point library in verilog
☆578Updated 2 years ago
Alternatives and similar repositories for fpu:
Users that are interested in fpu are comparing it to the libraries listed below
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,240Updated this week
- Bus bridges and other odds and ends☆526Updated last month
- Verilog AXI stream components for FPGA implementation☆791Updated 3 weeks ago
- Verilog UART☆461Updated 3 weeks ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆315Updated 10 months ago
- Common SystemVerilog components☆590Updated last week
- Various HDL (Verilog) IP Cores☆760Updated 3 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆426Updated 3 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆563Updated 7 years ago
- lowRISC Style Guides☆400Updated 6 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,028Updated last month
- Verilog AXI components for FPGA implementation☆1,655Updated 3 weeks ago
- 32-bit Superscalar RISC-V CPU☆972Updated 3 years ago
- SystemVerilog to Verilog conversion☆604Updated this week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆410Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆560Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆461Updated last month
- Verilog PCI express components☆1,247Updated 10 months ago
- Verilog I2C interface for FPGA implementation☆591Updated 3 weeks ago
- Verilog library for ASIC and FPGA designers☆1,261Updated 10 months ago
- AMBA bus lecture material☆412Updated 5 years ago
- The UVM written in Python☆415Updated 2 months ago
- An abstraction library for interfacing EDA tools☆670Updated this week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆484Updated 3 months ago
- RISC-V Formal Verification Framework☆598Updated 2 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆506Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆563Updated 7 months ago
- A template project for beginning new Chisel work☆623Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆904Updated 4 months ago
- AMBA AXI VIP☆387Updated 8 months ago