synthesiseable ieee 754 floating point library in verilog
☆763Mar 13, 2023Updated 3 years ago
Alternatives and similar repositories for fpu
Users that are interested in fpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- IEEE 754 floating point unit in Verilog☆154May 20, 2016Updated 10 years ago
- Mathematical Functions in Verilog☆101Mar 7, 2021Updated 5 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆648Updated this week
- ☆62Feb 18, 2019Updated 7 years ago
- Verilog AXI components for FPGA implementation☆2,168Feb 27, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 32-bit Superscalar RISC-V CPU☆1,329Sep 18, 2021Updated 5 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,742Updated this week
- IC implementation of Systolic Array for TPU☆382Oct 21, 2024Updated 2 years ago
- ☆394Aug 19, 2026Updated 2 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆691Updated this week
- Verilog library for ASIC and FPGA designers☆1,440May 8, 2024Updated 2 years ago
- double_fpu_verilog☆22Jul 17, 2014Updated 12 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆644Oct 10, 2021Updated 5 years ago
- Verilog PCI express components☆1,675Apr 26, 2024Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆84Jul 18, 2026Updated 3 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,184Updated this week
- Must-have verilog systemverilog modules☆2,030Mar 12, 2026Updated 7 months ago
- AMBA bus lecture material☆562Jan 21, 2020Updated 6 years ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 9 years ago
- Basic floating-point components for RISC-V processors☆69Dec 4, 2019Updated 6 years ago
- Common SystemVerilog components☆812Sep 18, 2026Updated last month
- Various HDL (Verilog) IP Cores☆939Jul 1, 2021Updated 5 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆254Oct 26, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- The Ultra-Low Power RISC-V Core☆1,969Sep 25, 2026Updated last month
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- RISC-V CPU Core☆454Jun 24, 2025Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆125Apr 3, 2026Updated 7 months ago
- ☆2,372Updated this week
- Verilog UART☆591Feb 27, 2025Updated last year
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,398Sep 7, 2026Updated last month
- RTL, Cmodel, and testbench for NVDLA☆2,195Mar 2, 2022Updated 4 years ago
- Verilog AXI stream components for FPGA implementation☆923Feb 27, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verilog Configurable Cache☆197Sep 21, 2026Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,316Updated this week
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆104Apr 30, 2019Updated 7 years ago
- Verilog I2C interface for FPGA implementation☆731Feb 27, 2025Updated last year
- Berkeley's Spatial Array Generator☆1,545Updated this week
- GEMM and GEMM-Ops accelerator for PULP systems☆126Oct 22, 2026Updated last week
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆241Sep 14, 2023Updated 3 years ago