dawsonjon / fpuLinks
synthesiseable ieee 754 floating point library in verilog
☆688Updated 2 years ago
Alternatives and similar repositories for fpu
Users that are interested in fpu are comparing it to the libraries listed below
Sorting:
- Common SystemVerilog components☆672Updated 2 weeks ago
- Bus bridges and other odds and ends☆603Updated 7 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,405Updated this week
- Verilog AXI stream components for FPGA implementation☆840Updated 8 months ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆388Updated 2 months ago
- SystemVerilog to Verilog conversion☆671Updated 2 weeks ago
- A DDR3 memory controller in Verilog for various FPGAs☆528Updated 4 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆616Updated this week
- Various HDL (Verilog) IP Cores☆842Updated 4 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆539Updated 3 weeks ago
- Verilog UART☆514Updated 8 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆446Updated 6 months ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆597Updated 7 years ago
- lowRISC Style Guides☆463Updated last week
- AMBA bus lecture material☆475Updated 5 years ago
- 32-bit Superscalar RISC-V CPU☆1,121Updated 4 years ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆520Updated 11 months ago
- An open-source static random access memory (SRAM) compiler.☆959Updated 3 weeks ago
- Verilog I2C interface for FPGA implementation☆656Updated 8 months ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆459Updated this week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆756Updated last year
- Verilog AXI components for FPGA implementation☆1,841Updated 8 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,138Updated 5 months ago
- Verilog SDRAM memory controller☆350Updated 8 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆579Updated 3 years ago
- Support for Rocket Chip on Zynq FPGAs☆412Updated 6 years ago
- ☆354Updated 2 months ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,162Updated last week
- training labs and examples☆435Updated 3 years ago
- Verilog library for ASIC and FPGA designers☆1,354Updated last year