BaseJump STL: A Standard Template Library for SystemVerilog
☆668May 11, 2026Updated 2 weeks ago
Alternatives and similar repositories for basejump_stl
Users that are interested in basejump_stl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Linux-capable RISC-V multicore for and by the world☆803Apr 24, 2026Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆291Apr 30, 2026Updated 3 weeks ago
- Common SystemVerilog components☆751May 21, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,584May 19, 2026Updated last week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆460May 20, 2026Updated last week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- SystemVerilog to Verilog conversion☆730Mar 28, 2026Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆376Updated this week
- Verilog library for ASIC and FPGA designers☆1,419May 8, 2024Updated 2 years ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆453Apr 5, 2026Updated last month
- The OpenPiton Platform☆791Feb 25, 2026Updated 3 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,849Mar 13, 2026Updated 2 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,947Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,883May 7, 2026Updated 3 weeks ago
- An open-source static random access memory (SRAM) compiler.☆1,065May 15, 2026Updated 2 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆38Mar 15, 2026Updated 2 months ago
- Verilog Configurable Cache☆198May 21, 2026Updated last week
- SystemVerilog compiler and language services☆1,049Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆981Nov 15, 2024Updated last year
- An abstraction library for interfacing EDA tools☆770Apr 24, 2026Updated last month
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,175Feb 21, 2026Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆295May 12, 2026Updated 2 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆606Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆472Mar 30, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆412May 19, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,417May 10, 2026Updated 2 weeks ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆607Jan 3, 2026Updated 4 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,235Apr 17, 2026Updated last month
- Hardware Description Languages☆1,148Apr 6, 2026Updated last month
- cocotb: Python-based chip (RTL) verification☆2,379May 22, 2026Updated last week
- Generic Register Interface (contains various adapters)☆140May 15, 2026Updated 2 weeks ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆256Updated this week
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆319May 20, 2026Updated last week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆318Mar 6, 2026Updated 2 months ago
- VeeR EH1 core☆945May 29, 2023Updated 3 years ago
- Random instruction generator for RISC-V processor verification☆1,303Apr 3, 2026Updated last month
- A dependency management tool for hardware projects.☆370May 22, 2026Updated last week
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆719Updated this week
- 32-bit Superscalar RISC-V CPU☆1,248Sep 18, 2021Updated 4 years ago
- Modular hardware build system☆1,160Updated this week