BaseJump STL: A Standard Template Library for SystemVerilog
☆654Jan 19, 2026Updated 2 months ago
Alternatives and similar repositories for basejump_stl
Users that are interested in basejump_stl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Linux-capable RISC-V multicore for and by the world☆787Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆285Feb 20, 2026Updated last month
- Common SystemVerilog components☆728Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,528Mar 18, 2026Updated last week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆454Mar 8, 2026Updated 3 weeks ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- SystemVerilog to Verilog conversion☆710Nov 24, 2025Updated 4 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆369Updated this week
- Verilog library for ASIC and FPGA designers☆1,400May 8, 2024Updated last year
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆446Mar 6, 2026Updated 3 weeks ago
- The OpenPiton Platform☆779Feb 25, 2026Updated last month
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,797Mar 13, 2026Updated 2 weeks ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,851Mar 20, 2026Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,814Feb 17, 2026Updated last month
- An open-source static random access memory (SRAM) compiler.☆1,024Mar 12, 2026Updated 2 weeks ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆38Mar 15, 2026Updated 2 weeks ago
- Verilog Configurable Cache☆193Mar 9, 2026Updated 2 weeks ago
- SystemVerilog compiler and language services☆989Mar 22, 2026Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆973Nov 15, 2024Updated last year
- An abstraction library for interfacing EDA tools☆756Updated this week
- A Fast, Low-Overhead On-chip Network☆272Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,159Feb 21, 2026Updated last month
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆468Nov 4, 2025Updated 4 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆407Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆580Mar 11, 2026Updated 2 weeks ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,398Feb 13, 2026Updated last month
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆597Jan 3, 2026Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,197May 26, 2025Updated 10 months ago
- Hardware Description Languages☆1,131Mar 17, 2026Updated last week
- cocotb: Python-based chip (RTL) verification☆2,289Mar 19, 2026Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆252Feb 22, 2026Updated last month
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated last month
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆315Feb 11, 2026Updated last month
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆315Mar 6, 2026Updated 3 weeks ago
- VeeR EH1 core☆931May 29, 2023Updated 2 years ago
- Random instruction generator for RISC-V processor verification☆1,265Mar 5, 2026Updated 3 weeks ago
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆710Mar 22, 2026Updated last week
- 32-bit Superscalar RISC-V CPU☆1,207Sep 18, 2021Updated 4 years ago
- A dependency management tool for hardware projects.☆357Mar 21, 2026Updated last week
- Modular hardware build system☆1,134Updated this week