YutaPic / FPULinks
For CPU experiment
☆14Updated 4 years ago
Alternatives and similar repositories for FPU
Users that are interested in FPU are comparing it to the libraries listed below
Sorting:
- ☆57Updated 6 years ago
- ☆90Updated 2 weeks ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆114Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆77Updated last month
- cycle accurate Network-on-Chip Simulator☆31Updated this week
- ☆61Updated 8 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆49Updated 2 weeks ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Floating point modules for CHISEL☆32Updated 11 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- ☆37Updated 2 months ago
- An open-source UCIe controller implementation☆81Updated this week
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Updated 2 weeks ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆46Updated last year
- ☆41Updated 9 months ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆19Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆24Updated 4 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆30Updated 4 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- RISC-V Matrix Specification☆24Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 6 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- matrix-coprocessor for RISC-V☆26Updated 3 weeks ago
- The official NaplesPU hardware code repository☆21Updated 6 years ago
- Chisel RISC-V Vector 1.0 Implementation☆126Updated 3 months ago