Verilog library for ASIC and FPGA designers
☆1,431May 8, 2024Updated 2 years ago
Alternatives and similar repositories for oh
Users that are interested in oh are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Must-have verilog systemverilog modules☆1,989Mar 12, 2026Updated 3 months ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆626Mar 15, 2018Updated 8 years ago
- Verilog AXI components for FPGA implementation☆2,082Feb 27, 2025Updated last year
- Verilog Ethernet components for FPGA implementation☆3,020Feb 27, 2025Updated last year
- HDL libraries and projects☆1,957Updated this week
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- BaseJump STL: A Standard Template Library for SystemVerilog☆673Updated this week
- Various HDL (Verilog) IP Cores☆915Jul 1, 2021Updated 5 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,429Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,616Updated this week
- Verilog PCI express components☆1,620Apr 26, 2024Updated 2 years ago
- Verilog AXI stream components for FPGA implementation☆900Feb 27, 2025Updated last year
- A small, light weight, RISC CPU soft core☆1,559Dec 8, 2025Updated 7 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,248Jun 27, 2024Updated 2 years ago
- Common SystemVerilog components☆764Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- An abstraction library for interfacing EDA tools☆774Jun 30, 2026Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,997Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,185Feb 11, 2026Updated 4 months ago
- mor1kx - an OpenRISC 1000 processor IP core☆586Jun 6, 2026Updated last month
- Hardware Description Languages☆1,158Updated this week
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,579May 12, 2026Updated last month
- An Open-source FPGA IP Generator☆1,122Updated this week
- Bus bridges and other odds and ends☆685Jun 2, 2026Updated last month
- An open source library for image processing on FPGA.☆634Jun 16, 2015Updated 11 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- cocotb: Python-based chip (RTL) verification☆2,430Updated this week
- SystemVerilog to Verilog conversion☆739Mar 28, 2026Updated 3 months ago
- An open-source static random access memory (SRAM) compiler.☆1,086Jun 27, 2026Updated last week
- RTL, Cmodel, and testbench for NVDLA☆2,114Mar 2, 2022Updated 4 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆689Jul 16, 2025Updated 11 months ago
- GPGPU microprocessor architecture☆2,204Nov 8, 2024Updated last year
- SERV - The SErial RISC-V CPU☆1,826Jun 17, 2026Updated 3 weeks ago
- Verilog I2C interface for FPGA implementation☆707Feb 27, 2025Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆988Nov 15, 2024Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Yosys Open SYnthesis Suite☆4,566Updated this week
- Parallella board design files☆421Feb 12, 2022Updated 4 years ago
- RISC-V CPU Core☆441Jun 24, 2025Updated last year
- VeeR EH1 core☆952May 29, 2023Updated 3 years ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆468Sep 13, 2024Updated last year
- Scala based HDL☆2,012Jun 20, 2026Updated 2 weeks ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆798Jun 15, 2024Updated 2 years ago