Alternatives and similar repositories for oh

Users that are interested in oh are comparing it to the libraries listed below

• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆868Updated 4 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,469Updated last month
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,518Updated last year
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆612Updated 7 years ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,502Updated last month
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆857Updated 10 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,162Updated 8 months ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,224Updated last week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,385Updated 2 weeks ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,933Updated 10 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆680Updated 6 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆959Updated last year
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆919Updated 2 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,746Updated this week
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆1,002Updated last year
• KastnerRG / riffa
  The RIFFA development repository
  ☆860Updated last year
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆676Updated 10 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆713Updated 2 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆530Updated 10 months ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,987Updated last month
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,173Updated 4 years ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,192Updated this week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,040Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,740Updated 3 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆629Updated 9 months ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆812Updated 2 weeks ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,243Updated 3 months ago
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆600Updated 5 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆700Updated last month
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,910Updated this week