Alternatives and similar repositories for oh

Users that are interested in oh are comparing it to the libraries listed below

• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,353Updated last week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,449Updated last week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,325Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆828Updated 4 years ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,406Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,109Updated 2 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆819Updated 5 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆674Updated last month
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,795Updated 5 months ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆593Updated 7 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,609Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆889Updated 2 years ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,058Updated this week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,132Updated this week
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆971Updated last year
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,153Updated 2 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆926Updated 9 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,086Updated 3 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆664Updated 2 years ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆981Updated last week
• KastnerRG / riffa
  The RIFFA development repository
  ☆839Updated last year
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆582Updated 4 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆502Updated 5 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆895Updated 4 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆640Updated 5 months ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆984Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆649Updated this week
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆872Updated 5 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆719Updated 5 months ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆585Updated 3 weeks ago