taneroksuz / fpu
IEEE 754 floating point library in system-verilog and vhdl
☆53Updated 3 months ago
Related projects: ⓘ
- A Fast, Low-Overhead On-chip Network☆115Updated this week
- Xilinx AXI VIP example of use☆29Updated 3 years ago
- Basic floating-point components for RISC-V processors☆62Updated 4 years ago
- ☆44Updated 3 years ago
- Mathematical Functions in Verilog☆82Updated 3 years ago
- SDRAM controller with AXI4 interface☆75Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆43Updated 3 months ago
- General Purpose AXI Direct Memory Access☆44Updated 4 months ago
- UART -> AXI Bridge☆52Updated 3 years ago
- A simple DDR3 memory controller☆49Updated last year
- AXI4 and AXI4-Lite interface definitions☆82Updated 3 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- round robin arbiter☆66Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆57Updated 4 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆26Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆57Updated 3 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆66Updated 6 years ago
- ☆35Updated 5 years ago
- ☆24Updated 5 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆48Updated 3 weeks ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆51Updated 8 months ago
- Two Level Cache Controller implementation in Verilog HDL☆31Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆53Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆136Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆58Updated last year
- Repository gathering basic modules for CDC purpose☆49Updated 4 years ago
- Vector processor for RISC-V vector ISA☆104Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆65Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆112Updated 3 months ago