alexforencich / verilog-uartLinks
Verilog UART
☆497Updated 5 months ago
Alternatives and similar repositories for verilog-uart
Users that are interested in verilog-uart are comparing it to the libraries listed below
Sorting:
- Verilog I2C interface for FPGA implementation☆635Updated 5 months ago
- Various HDL (Verilog) IP Cores☆823Updated 4 years ago
- Verilog AXI stream components for FPGA implementation☆817Updated 5 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆497Updated 3 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆357Updated last year
- SPI Master for FPGA - VHDL and Verilog☆297Updated last year
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆590Updated 7 years ago
- Bus bridges and other odds and ends☆576Updated 3 months ago
- Verilog SDRAM memory controller☆337Updated 8 years ago
- training labs and examples☆431Updated 3 years ago
- Verilog UART☆177Updated 12 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,339Updated last week
- SPI Slave for FPGA in Verilog and VHDL☆207Updated last year
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆316Updated last month
- ☆627Updated last week
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆509Updated 2 years ago
- AMBA bus lecture material☆453Updated 5 years ago
- AXI interface modules for Cocotb☆276Updated last year
- AMBA AXI VIP☆413Updated last year
- Common SystemVerilog components☆637Updated last week
- Verilog PCI express components☆1,390Updated last year
- Contains the code examples from The UVM Primer Book sorted by chapters.☆559Updated 3 years ago
- The RIFFA development repository☆839Updated last year
- synthesiseable ieee 754 floating point library in verilog☆661Updated 2 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆210Updated 2 years ago
- Verilog AXI components for FPGA implementation☆1,779Updated 5 months ago
- lowRISC Style Guides☆445Updated last month
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆272Updated 5 years ago
- Reference examples and short projects using UVM Methodology☆276Updated 3 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆436Updated 2 months ago