Verilog UART
☆574Feb 27, 2025Updated last year
Alternatives and similar repositories for verilog-uart
Users that are interested in verilog-uart are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog I2C interface for FPGA implementation☆710Feb 27, 2025Updated last year
- Verilog UART☆202Jun 4, 2013Updated 13 years ago
- Verilog AXI stream components for FPGA implementation☆906Feb 27, 2025Updated last year
- Verilog AXI components for FPGA implementation☆2,097Feb 27, 2025Updated last year
- Verilog Ethernet components for FPGA implementation☆3,042Feb 27, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verilog digital signal processing components☆187Oct 30, 2022Updated 3 years ago
- Verilog PCI express components☆1,628Apr 26, 2024Updated 2 years ago
- A simple, basic, formally verified UART controller☆343Jan 29, 2024Updated 2 years ago
- Verilog wishbone components☆133Jan 5, 2024Updated 2 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆162Feb 27, 2025Updated last year
- Various HDL (Verilog) IP Cores☆926Jul 1, 2021Updated 5 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆625Mar 15, 2018Updated 8 years ago
- Various utilities for working with FPGAs☆13Mar 30, 2016Updated 10 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆467Feb 13, 2026Updated 5 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆339Sep 14, 2023Updated 2 years ago
- A simple implementation of a UART modem in Verilog.☆192Nov 10, 2021Updated 4 years ago
- Verilog implementation of Mersenne Twister PRNG☆31Jun 20, 2018Updated 8 years ago
- Must-have verilog systemverilog modules☆1,999Mar 12, 2026Updated 4 months ago
- AMBA bus lecture material☆543Jan 21, 2020Updated 6 years ago
- Verilog library for ASIC and FPGA designers☆1,435May 8, 2024Updated 2 years ago
- synthesiseable ieee 754 floating point library in verilog☆745Mar 13, 2023Updated 3 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆617Oct 10, 2021Updated 4 years ago
- Verilog Content Addressable Memory Module☆118Mar 2, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Verilog FT245 to AXI stream interface☆29Jun 20, 2018Updated 8 years ago
- SPI Slave for FPGA in Verilog and VHDL☆233May 11, 2024Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆120Apr 27, 2024Updated 2 years ago
- Verilog SDRAM memory controller☆375May 13, 2017Updated 9 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,631Updated this week
- HDL libraries and projects☆1,980Updated this week
- UART models for cocotb☆35Sep 7, 2025Updated 10 months ago
- Open source FPGA-based NIC and platform for in-network compute☆68Aug 21, 2025Updated 11 months ago
- A small, light weight, RISC CPU soft core☆1,569Dec 8, 2025Updated 7 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,589May 12, 2026Updated 2 months ago
- Generic Register Interface (contains various adapters)☆141Updated this week
- AXI interface modules for Cocotb☆344Mar 13, 2026Updated 4 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,282Jun 27, 2024Updated 2 years ago
- Ethernet interface modules for Cocotb☆80Jun 20, 2026Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆136Jul 11, 2025Updated last year
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆20Aug 6, 2025Updated 11 months ago