akilm / FPU-IEEE-754
Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Square Root Operations based on the IEEE-754 standard for floating point numbers
☆47Updated 6 months ago
Alternatives and similar repositories for FPU-IEEE-754:
Users that are interested in FPU-IEEE-754 are comparing it to the libraries listed below
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated last month
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆88Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆45Updated last month
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- ☆29Updated 5 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆51Updated this week
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆72Updated last week
- ☆53Updated 4 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆44Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated 2 weeks ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- A verilog implementation for Network-on-Chip☆71Updated 7 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆121Updated 6 years ago
- Xilinx AXI VIP example of use☆33Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆54Updated 10 months ago
- Vector processor for RISC-V vector ISA☆113Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆169Updated last week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆160Updated 3 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆23Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 5 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆54Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆22Updated 11 months ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆39Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆32Updated 2 years ago