akilm / FPU-IEEE-754
Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Square Root Operations based on the IEEE-754 standard for floating point numbers
☆49Updated 7 months ago
Alternatives and similar repositories for FPU-IEEE-754:
Users that are interested in FPU-IEEE-754 are comparing it to the libraries listed below
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆89Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆41Updated 4 years ago
- ☆31Updated 5 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 2 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆48Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆123Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆69Updated last year
- ☆41Updated 6 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆81Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆72Updated last month
- SystemVerilog modules and classes commonly used for verification☆46Updated 2 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆82Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆66Updated this week
- ☆53Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆25Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆22Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆136Updated 3 weeks ago
- ☆12Updated 3 weeks ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆163Updated 3 months ago