Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Square Root Operations based on the IEEE-754 standard for floating point numbers
☆77Aug 10, 2024Updated 2 years ago
Alternatives and similar repositories for FPU-IEEE-754
Users that are interested in FPU-IEEE-754 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- IEEE 754 floating point unit in Verilog☆154May 20, 2016Updated 10 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆33Mar 13, 2025Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- 简单的未优化的SRT除法器☆13Jun 16, 2024Updated 2 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆15Sep 29, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆85Jul 18, 2026Updated 3 months ago
- This is the verilog implementation of IEEE 754 32 bit floating point multiplier☆12Jul 12, 2020Updated 6 years ago
- synthesiseable ieee 754 floating point library in verilog☆763Mar 13, 2023Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆104Apr 30, 2019Updated 7 years ago
- An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) at UMJI.☆11Dec 28, 2020Updated 5 years ago
- An extention of pytorch for low precision training / inference☆10Aug 28, 2023Updated 3 years ago
- all kind of notes, I maybe sort this in the future☆13Aug 29, 2025Updated last year
- A RTL Synthesizer that can convert Verilog HDL into transistor-level netlist which can be simulated by Spice☆13Jan 4, 2025Updated last year
- ☆62Feb 18, 2019Updated 7 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Unit Tested implementation of SPI protocol in verilog☆11Nov 13, 2021Updated 4 years ago
- Floating-point matrix multiplication implementation (arbitrary precision)☆18Aug 3, 2021Updated 5 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- A simple 8086-CPU simulator using Verilog and Quartus II☆12Jul 9, 2018Updated 8 years ago
- This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with single port sync RAM.☆11Jan 31, 2025Updated last year
- ☆12Mar 24, 2023Updated 3 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆29Oct 31, 2021Updated 5 years ago
- Implementing Different Adder Structures in Verilog☆78Sep 3, 2019Updated 7 years ago
- A tool for creating HDL-Schematics☆10Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- ☆22Aug 4, 2022Updated 4 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- ☆10Mar 11, 2017Updated 9 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆651Updated this week
- SystemC training aimed at TLM.☆39Jul 31, 2020Updated 6 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆40Jul 23, 2023Updated 3 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆23Aug 6, 2025Updated last year
- ☆396Aug 19, 2026Updated 2 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Residual vector quantization for KV cache compression in large language model☆12Oct 22, 2024Updated 2 years ago
- ☆13Jul 2, 2016Updated 10 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆125Apr 3, 2026Updated 7 months ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆42Jul 1, 2023Updated 3 years ago
- This repository provides a Linux kernel driver for AXI UART Lite accessed via PCIe XDMA. It enables efficient DMA-based UART communicatio…☆16May 2, 2025Updated last year
- RISC-V 64 CPU☆10Oct 4, 2025Updated last year