akilm / FPU-IEEE-754
Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Square Root Operations based on the IEEE-754 standard for floating point numbers
☆53Updated 9 months ago
Alternatives and similar repositories for FPU-IEEE-754
Users that are interested in FPU-IEEE-754 are comparing it to the libraries listed below
Sorting:
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆100Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆74Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆77Updated this week
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago
- General Purpose AXI Direct Memory Access☆49Updated last year
- ☆33Updated 6 years ago
- A Fast, Low-Overhead On-chip Network☆201Updated this week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last month
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆53Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆147Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆90Updated this week
- Two Level Cache Controller implementation in Verilog HDL☆45Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆84Updated 6 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆40Updated 5 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆45Updated 10 months ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆53Updated 3 years ago
- ☆42Updated 8 months ago
- ☆56Updated 4 years ago
- Verilog implementation of Softmax function☆65Updated 2 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆85Updated last year
- Introductory course into static timing analysis (STA).☆93Updated 2 weeks ago
- This is a tutorial on standard digital design flow☆76Updated 3 years ago