akilm / FPU-IEEE-754Links
Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Square Root Operations based on the IEEE-754 standard for floating point numbers
☆60Updated 11 months ago
Alternatives and similar repositories for FPU-IEEE-754
Users that are interested in FPU-IEEE-754 are comparing it to the libraries listed below
Sorting:
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆173Updated 8 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆88Updated 6 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆127Updated 7 years ago
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated 2 weeks ago
- A Fast, Low-Overhead On-chip Network☆220Updated last week
- General Purpose AXI Direct Memory Access☆57Updated last year
- Vector processor for RISC-V vector ISA☆122Updated 4 years ago
- A verilog implementation for Network-on-Chip☆75Updated 7 years ago
- ☆34Updated 6 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆174Updated 3 weeks ago
- IEEE 754 floating point unit in Verilog☆145Updated 9 years ago
- An AXI4 crossbar implementation in SystemVerilog☆166Updated last month
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆51Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 10 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated 2 weeks ago
- ☆63Updated 4 years ago
- ☆52Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆90Updated 7 months ago
- Simple cache design implementation in verilog☆49Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆105Updated 2 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆58Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆127Updated 2 weeks ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago