Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Square Root Operations based on the IEEE-754 standard for floating point numbers
☆74Aug 10, 2024Updated 2 years ago
Alternatives and similar repositories for FPU-IEEE-754
Users that are interested in FPU-IEEE-754 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- IEEE 754 floating point unit in Verilog☆152May 20, 2016Updated 10 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆33Mar 13, 2025Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆83Jul 18, 2026Updated last month
- all kind of notes, I maybe sort this in the future☆13Aug 29, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- synthesiseable ieee 754 floating point library in verilog☆756Mar 13, 2023Updated 3 years ago
- Floating-point matrix multiplication implementation (arbitrary precision)☆18Aug 3, 2021Updated 5 years ago
- An extention of pytorch for low precision training / inference☆10Aug 28, 2023Updated 3 years ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆17Nov 19, 2019Updated 6 years ago
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated 2 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆103Apr 30, 2019Updated 7 years ago
- Residual vector quantization for KV cache compression in large language model☆12Oct 22, 2024Updated last year
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Implementing Different Adder Structures in Verilog☆77Sep 3, 2019Updated 7 years ago
- ☆21Aug 4, 2022Updated 4 years ago
- VHDL source file project for a hardware in the loop simulation of a permanen magnet motor with field oriented control design☆13Nov 22, 2022Updated 3 years ago
- ☆25Jun 25, 2026Updated 2 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆125Apr 3, 2026Updated 5 months ago
- A Verilog RTL model of a simple 8-bit RISC processor☆21Jan 15, 2019Updated 7 years ago
- ☆13Jul 2, 2016Updated 10 years ago
- ☆11Feb 11, 2019Updated 7 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆20Oct 18, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V 64 CPU☆10Oct 4, 2025Updated 11 months ago
- ☆27Mar 19, 2021Updated 5 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 3 years ago
- The Verilog source code for DRUM approximate multiplier.☆32May 4, 2023Updated 3 years ago
- A tool for modeling FSMs by VHDL or Verilog☆14Updated this week
- PyTorch implementation of D4PG with the SOTA IQN Critic instead of C51. Implementation includes also the extensions Munchausen RL and D2R…☆25Apr 7, 2021Updated 5 years ago
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 8 years ago
- ☆17Aug 16, 2023Updated 3 years ago
- An UVM example of UART☆20Aug 31, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆45May 5, 2023Updated 3 years ago
- ☆392Aug 19, 2026Updated 2 weeks ago
- Parametric GPIO Peripheral☆13Jan 30, 2025Updated last year
- Fake86 emulator redux☆15Jun 6, 2021Updated 5 years ago
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆62Nov 30, 2022Updated 3 years ago
- Minimalistic RV32I RISC-V Processor in System Verilog☆35Sep 19, 2023Updated 2 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Oct 8, 2020Updated 5 years ago