Alternatives and similar repositories for iob-cache

Users that are interested in iob-cache are comparing it to the libraries listed below

• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆221Updated 3 weeks ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆188Updated 2 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆126Updated 4 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆173Updated 9 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 4 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆174Updated last month
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆169Updated this week
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆125Updated 10 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆154Updated 9 months ago
• subbdue / systemverilog.io
  Code used in
  ☆193Updated 8 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆207Updated this week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated this week
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆100Updated 2 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆292Updated last year
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆254Updated 3 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆294Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆129Updated 7 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆139Updated last month
• chipsalliance / uvm-verilator
  ☆97Updated last year
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆126Updated 2 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆525Updated 2 weeks ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆263Updated 2 months ago
• ucb-bar / berkeley-hardfloat
  ☆336Updated 11 months ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆207Updated 2 weeks ago