IObundle / iob-cache
Verilog Configurable Cache
☆169Updated 2 months ago
Alternatives and similar repositories for iob-cache:
Users that are interested in iob-cache are comparing it to the libraries listed below
- RISC-V System on Chip Template☆156Updated this week
- A Fast, Low-Overhead On-chip Network☆165Updated this week
- Vector processor for RISC-V vector ISA☆113Updated 4 years ago
- An Open-Source Design and Verification Environment for RISC-V☆78Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆131Updated 2 months ago
- Network on Chip Implementation written in SytemVerilog☆165Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆159Updated 2 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆454Updated this week
- A dynamic verification library for Chisel.☆145Updated 3 months ago
- Instruction Set Generator initially contributed by Futurewei☆271Updated last year
- Generic Register Interface (contains various adapters)☆106Updated 4 months ago
- Various caches written in Verilog-HDL☆114Updated 9 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆204Updated 4 years ago
- A Chisel RTL generator for network-on-chip interconnects☆182Updated 2 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆118Updated this week
- AXI4 and AXI4-Lite interface definitions☆91Updated 4 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- VeeR EL2 Core☆263Updated this week
- Common SystemVerilog components☆570Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆243Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 3 months ago
- ☆86Updated last year
- ☆114Updated this week
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆88Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆241Updated 3 months ago
- RISC-V Verification Interface☆84Updated 5 months ago
- UVM 1.2 port to Python☆248Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆166Updated 6 months ago
- RISC-V Torture Test☆177Updated 7 months ago