Verilog Configurable Cache
☆196Mar 9, 2026Updated last month
Alternatives and similar repositories for iob-cache
Users that are interested in iob-cache are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V System on Chip Template☆161Apr 2, 2026Updated 3 weeks ago
- Coarse Grained Reconfigurable Array☆20Apr 15, 2026Updated 2 weeks ago
- Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores☆13Feb 23, 2025Updated last year
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆14Dec 22, 2025Updated 4 months ago
- Running Linux on IOb-SoC-OpenCryptoHW☆15Aug 15, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Various caches written in Verilog-HDL☆129Apr 24, 2015Updated 11 years ago
- a Python framework for managing embedded HW/SW projects☆21Apr 14, 2026Updated 2 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆660Apr 7, 2026Updated 3 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,561Apr 22, 2026Updated last week
- Synthesizable and Parameterized Cache Controller in Verilog☆46Jun 13, 2023Updated 2 years ago
- Common SystemVerilog components☆738Apr 23, 2026Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆288Mar 30, 2026Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆594Apr 20, 2026Updated last week
- 32-bit Superscalar RISC-V CPU☆1,236Sep 18, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated 2 months ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 5 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆191Nov 18, 2024Updated last year
- Verilog AXI components for FPGA implementation☆2,030Feb 27, 2025Updated last year
- A Linux-capable RISC-V multicore for and by the world☆798Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆207Apr 8, 2026Updated 3 weeks ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,169Feb 21, 2026Updated 2 months ago
- Simple runtime for Pulp platforms☆52Feb 2, 2026Updated 2 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆231Aug 25, 2020Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Network on Chip Implementation written in SytemVerilog☆202Aug 27, 2022Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,221Apr 17, 2026Updated last week
- ☆29Feb 20, 2024Updated 2 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- ☆14Feb 24, 2025Updated last year
- AMBA AXI VIP☆457Jun 28, 2024Updated last year
- Repository gathering basic modules for CDC purpose☆60Dec 31, 2019Updated 6 years ago
- Two Level Cache Controller implementation in Verilog HDL☆62Jul 9, 2020Updated 5 years ago
- Basic Common Modules☆48Mar 18, 2026Updated last month
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆42Oct 23, 2016Updated 9 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆117Sep 24, 2025Updated 7 months ago
- Bus bridges and other odds and ends☆662Mar 10, 2026Updated last month
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆243Jul 16, 2023Updated 2 years ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆292Apr 22, 2026Updated last week