Alternatives and similar repositories for sv2v

Users that are interested in sv2v are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆637Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆593Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆576Updated 3 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆512Updated 5 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆718Updated 3 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆445Updated last month
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆462Updated last week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆704Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆400Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆334Updated last week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆800Updated this week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆399Updated 6 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆505Updated 8 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆443Updated 3 weeks ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆436Updated 2 months ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆628Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,339Updated last week
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆541Updated last year
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆569Updated 3 weeks ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆497Updated 3 years ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆928Updated last month
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆605Updated 3 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆321Updated 7 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆721Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆885Updated 2 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,098Updated 2 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆925Updated 8 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆292Updated last week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,066Updated 3 years ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆964Updated this week