Alternatives and similar repositories for sv2v:

Users that are interested in sv2v are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆590Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆560Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆461Updated last month
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆309Updated this week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆426Updated 3 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆526Updated last month
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆431Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆382Updated 2 weeks ago
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆518Updated last year
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆669Updated 3 weeks ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,240Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆400Updated 6 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆410Updated last week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆376Updated 2 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆506Updated this week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆670Updated this week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆308Updated 3 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆598Updated 2 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆415Updated 2 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆578Updated 2 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆268Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆967Updated 3 years ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆602Updated this week
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆428Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆862Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆246Updated last month
• RoaLogic / RV12
  RISC-V CPU Core
  ☆317Updated 9 months ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆904Updated 4 months ago
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆380Updated this week
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆637Updated last week