Alternatives and similar repositories for sv2v:

Users that are interested in sv2v are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆608Updated 3 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆570Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆453Updated 3 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆551Updated 3 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆485Updated 2 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆599Updated 3 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆688Updated last week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆528Updated 3 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆425Updated 7 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆318Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆388Updated 3 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆682Updated this week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆894Updated last month
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆445Updated 3 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,267Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,276Updated 2 weeks ago
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆736Updated last week
• pyuvm / pyuvm
  The UVM written in Python
  ☆423Updated 3 weeks ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆386Updated 4 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,063Updated 2 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆274Updated last week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆421Updated last month
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆522Updated last year
• SpinalHDL / NaxRiscv
  ☆283Updated last month
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆624Updated 2 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆875Updated last year
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆612Updated last month
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆300Updated last year
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆427Updated 7 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆324Updated 11 months ago