Verilog PCI express components
☆1,543Apr 26, 2024Updated last year
Alternatives and similar repositories for verilog-pcie
Users that are interested in verilog-pcie are comparing it to the libraries listed below
Sorting:
- Verilog AXI components for FPGA implementation☆1,970Feb 27, 2025Updated last year
- Verilog Ethernet components for FPGA implementation☆2,865Feb 27, 2025Updated last year
- Open source FPGA-based NIC and platform for in-network compute☆2,222Jul 5, 2024Updated last year
- Small footprint and configurable PCIe core☆666Updated this week
- Verilog AXI stream components for FPGA implementation☆865Feb 27, 2025Updated last year
- PCI express simulation framework for Cocotb☆195Sep 8, 2025Updated 6 months ago
- The RIFFA development repository☆865Jun 11, 2024Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,510Feb 25, 2026Updated last week
- Verilog I2C interface for FPGA implementation☆686Feb 27, 2025Updated last year
- Must-have verilog systemverilog modules☆1,935Feb 19, 2026Updated 2 weeks ago
- HDL libraries and projects☆1,866Updated this week
- A DDR3 memory controller in Verilog for various FPGAs☆572Oct 10, 2021Updated 4 years ago
- Verilog library for ASIC and FPGA designers☆1,395May 8, 2024Updated last year
- Verilog UART☆536Feb 27, 2025Updated last year
- cocotb: Python-based chip (RTL) verification☆2,271Updated this week
- Common SystemVerilog components☆718Feb 26, 2026Updated last week
- AXI interface modules for Cocotb☆315Sep 30, 2025Updated 5 months ago
- Various HDL (Verilog) IP Cores☆876Jul 1, 2021Updated 4 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆787Sep 14, 2023Updated 2 years ago
- Bus bridges and other odds and ends☆644Apr 14, 2025Updated 10 months ago
- AMBA bus lecture material☆515Jan 21, 2020Updated 6 years ago
- Example designs for FPGA Drive FMC☆287Feb 28, 2026Updated last week
- PCIE 5.0 Graduation project (Verification Team)☆102Jan 27, 2024Updated 2 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆649Jan 19, 2026Updated last month
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆899Updated this week
- Verilog digital signal processing components☆171Oct 30, 2022Updated 3 years ago
- AMBA AXI VIP☆448Jun 28, 2024Updated last year
- Fully parametrizable combinatorial parallel LFSR/CRC module☆161Feb 27, 2025Updated last year
- An Open-source FPGA IP Generator☆1,057Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,986Jun 27, 2024Updated last year
- 32-bit Superscalar RISC-V CPU☆1,183Sep 18, 2021Updated 4 years ago
- Opensource DDR3 Controller☆420Jan 18, 2026Updated last month
- Xilinx QDMA IP Drivers☆767Feb 26, 2026Updated last week
- ☆83Jun 27, 2022Updated 3 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,828Feb 25, 2026Updated last week
- Build your hardware, easily!☆3,747Updated this week
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆646Updated this week
- A small, light weight, RISC CPU soft core☆1,514Dec 8, 2025Updated 3 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,032Feb 11, 2026Updated 3 weeks ago