Alternatives and similar repositories for verilog-pcie

Users that are interested in verilog-pcie are comparing it to the libraries listed below

• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,762Updated 4 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,319Updated last week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆812Updated 4 months ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆838Updated last year
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆818Updated 4 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆625Updated 4 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,309Updated last year
• alexforencich / verilog-ethernet
  Verilog Ethernet components for FPGA implementation
  ☆2,619Updated 4 months ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆582Updated 7 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆493Updated 4 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆634Updated this week
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,806Updated 3 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,053Updated 3 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆492Updated 3 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆572Updated 2 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,136Updated last month
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,086Updated last month
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆971Updated last week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆884Updated 2 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,581Updated last week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,025Updated this week
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆657Updated 2 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆924Updated 7 months ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆448Updated 5 years ago
• WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆641Updated last year
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆354Updated last year
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆937Updated this week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆919Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆585Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆645Updated 2 weeks ago