alexforencich / verilog-i2c
Verilog I2C interface for FPGA implementation
☆575Updated 7 months ago
Alternatives and similar repositories for verilog-i2c:
Users that are interested in verilog-i2c are comparing it to the libraries listed below
- Various HDL (Verilog) IP Cores☆743Updated 3 years ago
- Verilog UART☆445Updated last year
- Verilog AXI stream components for FPGA implementation☆776Updated 6 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆408Updated 3 years ago
- Verilog PCI express components☆1,211Updated 9 months ago
- Verilog AXI components for FPGA implementation☆1,609Updated last year
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆300Updated 9 months ago
- SPI Master for FPGA - VHDL and Verilog☆269Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,203Updated 2 weeks ago
- ☆601Updated 7 months ago
- Bus bridges and other odds and ends☆520Updated 2 weeks ago
- Common SystemVerilog components☆572Updated 2 weeks ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆562Updated 6 years ago
- Verilog SDRAM memory controller☆316Updated 7 years ago
- The RIFFA development repository☆799Updated 8 months ago
- SPI Slave for FPGA in Verilog and VHDL☆192Updated 9 months ago
- AMBA bus lecture material☆403Updated 5 years ago
- Awesome ASIC design verification☆285Updated 3 years ago
- synthesiseable ieee 754 floating point library in verilog☆564Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,010Updated last week
- lowRISC Style Guides☆388Updated 5 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆264Updated 4 years ago
- AXI interface modules for Cocotb☆233Updated last year
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆568Updated 4 years ago
- Vivado诸多IP,包括图像处理等☆191Updated 6 months ago
- SystemVerilog to Verilog conversion☆590Updated this week
- 32-bit Superscalar RISC-V CPU☆943Updated 3 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆225Updated 2 years ago
- The UVM written in Python☆401Updated last month
- Opensource DDR3 Controller☆265Updated this week