Alternatives and similar repositories for verilog-i2c

Users that are interested in verilog-i2c are comparing it to the libraries listed below

• alexforencich / verilog-uart
  Verilog UART
  ☆506Updated 7 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆835Updated 4 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆831Updated 7 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆516Updated 3 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆383Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆589Updated 5 months ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆299Updated 2 years ago
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,435Updated last year
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆394Updated 3 weeks ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,377Updated last week
• Digilent / vivado-library
  ☆637Updated 2 months ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,822Updated 7 months ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆594Updated 7 years ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆849Updated last year
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆467Updated 5 years ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆345Updated 8 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆660Updated last week
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆214Updated last year
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆432Updated 3 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆455Updated this week
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆523Updated 2 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆288Updated 3 weeks ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆425Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆457Updated 3 months ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆571Updated 3 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆674Updated 2 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆323Updated 3 years ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆230Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆222Updated 2 years ago