Alternatives and similar repositories for verilog-i2c

Users that are interested in verilog-i2c are comparing it to the libraries listed below

• alexforencich / verilog-uart
  Verilog UART
  ☆514Updated 9 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆847Updated 4 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆529Updated 4 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆841Updated 9 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆392Updated 2 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆609Updated 7 months ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆351Updated 8 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆480Updated 2 weeks ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆309Updated 2 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,414Updated last week
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,460Updated last year
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆599Updated 7 years ago
• Digilent / vivado-library
  ☆650Updated 4 months ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆439Updated 3 years ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆853Updated last year
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,868Updated 9 months ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆540Updated 2 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆675Updated last week
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆482Updated 5 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆333Updated 3 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆215Updated last year
• pyuvm / pyuvm
  The UVM written in Python
  ☆483Updated last week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆298Updated 2 months ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆581Updated 3 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆430Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆468Updated 3 weeks ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆393Updated 5 months ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆413Updated last week
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆283Updated 3 years ago