dawsonjon / verilog-mathLinks
Mathematical Functions in Verilog
☆95Updated 4 years ago
Alternatives and similar repositories for verilog-math
Users that are interested in verilog-math are comparing it to the libraries listed below
Sorting:
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆70Updated 9 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆111Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆176Updated 10 months ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- SpinalHDL Hardware Math Library☆91Updated last year
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Verilog digital signal processing components☆156Updated 2 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 2 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43Updated 5 years ago
- An implementation of the CORDIC algorithm in Verilog.☆100Updated 6 years ago
- Altera Advanced Synthesis Cookbook 11.0☆107Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated this week
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆78Updated 2 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆89Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 3 months ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆95Updated this week
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- IP operations in verilog (simulation and implementation on ice40)☆60Updated 5 years ago
- Generate testbench for your verilog module.☆38Updated 7 years ago
- round robin arbiter☆75Updated 11 years ago
- General Purpose AXI Direct Memory Access☆59Updated last year
- Basic RISC-V Test SoC☆144Updated 6 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated 2 months ago