dawsonjon / verilog-math

Related projects ⓘ

Alternatives and complementary repositories for verilog-math

• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆76Updated 2 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆146Updated this week
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆78Updated 5 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆58Updated last month
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆138Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆93Updated last year
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆98Updated 3 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆137Updated 3 weeks ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆62Updated last year
• oprecomp / DDR4_controller
  ☆47Updated 3 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆81Updated 6 months ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆83Updated 2 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆133Updated 5 months ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆57Updated 3 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆68Updated 10 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆212Updated this week
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆107Updated 2 years ago
• FPGA-Research-Manchester / FABulous
  Fabric generator and CAD tools
  ☆148Updated last week
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆40Updated 4 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆54Updated 3 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆72Updated 12 years ago
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆142Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆115Updated last month
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆83Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆129Updated 2 weeks ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆78Updated 4 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆104Updated 5 years ago