Verilog AXI stream components for FPGA implementation
☆886Feb 27, 2025Updated last year
Alternatives and similar repositories for verilog-axis
Users that are interested in verilog-axis are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog AXI components for FPGA implementation☆2,030Feb 27, 2025Updated last year
- Verilog Ethernet components for FPGA implementation☆2,947Feb 27, 2025Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,566Apr 22, 2026Updated last week
- Verilog PCI express components☆1,591Apr 26, 2024Updated 2 years ago
- Verilog UART☆561Feb 27, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- AXI interface modules for Cocotb☆329Mar 13, 2026Updated last month
- Bus bridges and other odds and ends☆663Mar 10, 2026Updated last month
- Verilog I2C interface for FPGA implementation☆698Feb 27, 2025Updated last year
- Verilog digital signal processing components☆176Oct 30, 2022Updated 3 years ago
- Open source FPGA-based NIC and platform for in-network compute☆68Aug 21, 2025Updated 8 months ago
- Verilog library for ASIC and FPGA designers☆1,410May 8, 2024Updated last year
- HDL libraries and projects☆1,905Apr 27, 2026Updated last week
- Open source FPGA-based NIC and platform for in-network compute☆2,293Jul 5, 2024Updated last year
- cocotb: Python-based chip (RTL) verification☆2,354Apr 27, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Common SystemVerilog components☆738Apr 27, 2026Updated last week
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Feb 27, 2025Updated last year
- AMBA AXI VIP☆457Jun 28, 2024Updated last year
- Various HDL (Verilog) IP Cores☆897Jul 1, 2021Updated 4 years ago
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated 2 months ago
- Verilog wishbone components☆127Jan 5, 2024Updated 2 years ago
- Verilog Content Addressable Memory Module☆117Mar 2, 2022Updated 4 years ago
- Extensible FPGA control platform☆63Apr 28, 2023Updated 3 years ago
- Small footprint and configurable PCIe core☆685Apr 27, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The RIFFA development repository☆870Jun 11, 2024Updated last year
- Verilog FT245 to AXI stream interface☆29Jun 20, 2018Updated 7 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆150Mar 16, 2026Updated last month
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆448Feb 13, 2026Updated 2 months ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆915Apr 15, 2026Updated 2 weeks ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,127Jun 27, 2024Updated last year
- PCI express simulation framework for Cocotb☆203Sep 8, 2025Updated 7 months ago
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆604Jul 30, 2025Updated 9 months ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆727Apr 7, 2026Updated 3 weeks ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- AMBA bus lecture material☆531Jan 21, 2020Updated 6 years ago
- A huge VHDL library for FPGA and digital ASIC development☆457Updated this week
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆243Jul 16, 2023Updated 2 years ago
- Opensource DDR3 Controller☆428Jan 18, 2026Updated 3 months ago
- Code generation tool for control and status registers☆455Apr 19, 2026Updated 2 weeks ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,410Feb 13, 2026Updated 2 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆589Oct 10, 2021Updated 4 years ago