Alternatives and similar repositories for verilog-axis

Users that are interested in verilog-axis are comparing it to the libraries listed below

• alexforencich / verilog-uart
  Verilog UART
  ☆502Updated 5 months ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,795Updated 5 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,353Updated last week
• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,406Updated last year
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆640Updated 5 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆828Updated 4 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆582Updated 4 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆363Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆649Updated this week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆502Updated 3 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆456Updated 5 years ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆593Updated 7 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆564Updated 3 years ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆839Updated last year
• pyuvm / pyuvm
  The UVM written in Python
  ☆449Updated last month
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆345Updated 2 weeks ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆416Updated last year
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆664Updated 2 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆276Updated last year
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆367Updated last week
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆432Updated 3 years ago
• Digilent / vivado-library
  ☆631Updated 3 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆448Updated 2 months ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆316Updated 3 years ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,330Updated last year
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆438Updated 3 months ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆585Updated 3 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆598Updated last week
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆278Updated 3 years ago
• Xilinx / Vitis-HLS-Introductory-Examples
  ☆708Updated last month