dawsonjon / chips_vLinks
RISC-V System on Chip Builder
☆12Updated 5 years ago
Alternatives and similar repositories for chips_v
Users that are interested in chips_v are comparing it to the libraries listed below
Sorting:
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 7 months ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆21Updated 5 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated 2 weeks ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated last month
- SAR ADC on tiny tapeout☆43Updated 9 months ago
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆35Updated 5 months ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 6 years ago
- ☆33Updated 2 years ago
- A CIC filter implemented in Verilog☆23Updated 10 years ago
- Bitstream relocation and manipulation tool.☆49Updated 2 years ago
- general-cores☆21Updated 4 months ago
- Projects published on controlpaths.com and hackster.io☆42Updated 3 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated last week
- Small footprint and configurable HyperBus core☆13Updated 3 years ago
- ☆38Updated 2 years ago
- VHDL PCIe Transceiver☆31Updated 5 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Updated 6 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- Documenting the Lattice ECP5 bit-stream format.☆56Updated 2 years ago
- PicoRV☆43Updated 5 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Virtual Development Board☆64Updated 3 years ago
- high level VHDL floating point library for synthesis in fpga☆18Updated this week
- A padring generator for ASICs☆25Updated 2 years ago
- A current mode buck converter on the SKY130 PDK☆33Updated 4 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- Open Source AES☆31Updated last month
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Example of how to use UVM with Verilator☆27Updated 3 weeks ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆68Updated 2 months ago