Alternatives and similar repositories for chips_v

Users that are interested in chips_v are comparing it to the libraries listed below

• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆12Updated 2 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆22Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆59Updated 3 weeks ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆17Updated 2 months ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• tongchen126 / fpga_pcie_ethernet
  ☆16Updated 3 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆30Updated 4 years ago
• britovski / adder
  Adder in VHDL to test the digital flow using ghdl and GTKwave (front-end) and openlane (back-end). Translated from the original https://g…
  ☆11Updated 3 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆27Updated 5 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆26Updated 5 years ago
• AEW2015 / fpga-colab
  FPGA examples on Google Colab
  ☆22Updated last year
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆21Updated last year
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 7 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• enjoy-digital / xtrx_julia
  XTRX LiteX/LitePCIe based design for Julia Computing
  ☆26Updated last year
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆21Updated 5 years ago
• EEVengers / thunderscope_litex
  LiteX based FPGA gateware for Thunderscope.
  ☆21Updated last month
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆17Updated 2 months ago
• Digilent / Arty-A7-35-XADC
  ☆19Updated 4 years ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆13Updated 6 years ago
• lawrie / ulx3s_bit_streams
  Bit streams forthe Ulx3s ECP5 device
  ☆17Updated 2 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• machdyne / lowe
  Löwe FPGA Board
  ☆12Updated last year
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆43Updated 4 months ago
• merledu / symbiflow-magic
  This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.
  ☆10Updated 4 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆44Updated this week