jiegec / fpu-wrappers
Wrappers for open source FPU hardware implementations.
☆30Updated 10 months ago
Alternatives and similar repositories for fpu-wrappers:
Users that are interested in fpu-wrappers are comparing it to the libraries listed below
- ☆32Updated this week
- The 'missing header' for Chisel☆18Updated this week
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆25Updated last month
- Chisel library for Unum Type-III Posit Arithmetic☆36Updated 10 months ago
- Implements kernels with RISC-V Vector☆21Updated last year
- Run Rocket Chip on VCU128☆29Updated 2 months ago
- Intel Compiler for SystemC☆24Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆56Updated 3 years ago
- Lower chisel memories to SRAM macros☆12Updated 10 months ago
- A Rocket-Chip with a Dynamically Randomized LLC☆12Updated 5 months ago
- The experimental work to rewrite Chisel in pure Scala 3 and the Panama Project☆24Updated this week
- Hardware design with Chisel☆31Updated 2 years ago
- Open source high performance IEEE-754 floating unit☆67Updated 11 months ago
- This repo includes XiangShan's function units☆18Updated this week
- Open-source non-blocking L2 cache☆35Updated this week
- The RTL source for AnyCore RISC-V☆31Updated 2 years ago
- A libgloss replacement for RISC-V that supports HTIF☆28Updated 9 months ago
- A Rocket-based RISC-V superscalar in-order core☆29Updated 2 weeks ago
- Chisel Cheatsheet☆32Updated last year
- ☆17Updated 2 years ago
- Chisel RISC-V Vector 1.0 Implementation☆78Updated last week
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated last week
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated last week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- A prototype GUI for chisel-development☆52Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- The specification for the FIRRTL language☆51Updated this week
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆27Updated 11 years ago