jiegec / fpu-wrappersView external linksLinks
Wrappers for open source FPU hardware implementations.
☆37Nov 27, 2025Updated 2 months ago
Alternatives and similar repositories for fpu-wrappers
Users that are interested in fpu-wrappers are comparing it to the libraries listed below
Sorting:
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 2 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 5 months ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- List of SpinalHDL projects, libraries, and learning resources.☆25Jan 6, 2026Updated last month
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- Open source high performance IEEE-754 floating unit☆89Feb 26, 2024Updated last year
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Mar 29, 2013Updated 12 years ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- Open-source non-blocking L2 cache☆52Feb 3, 2026Updated last week
- A collection of notes related to RISC-V before they are processed and digested☆18Dec 19, 2017Updated 8 years ago
- chipyard in mill :P☆77Nov 20, 2023Updated 2 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆45Apr 2, 2025Updated 10 months ago
- ☆367Sep 12, 2025Updated 5 months ago
- A simple MIPS CPU for BUAA CO course (and now NSCSCC).☆10May 15, 2021Updated 4 years ago
- ☆12Feb 15, 2024Updated last year
- Posit Arithmetic Cores generated with FloPoCo☆28Jun 25, 2024Updated last year
- Intel Compiler for SystemC☆27Jun 1, 2023Updated 2 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated 2 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Jan 2, 2026Updated last month
- Verilog Configurable Cache☆192Jan 28, 2026Updated 2 weeks ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- ☆15Feb 5, 2026Updated last week
- ☆13Feb 13, 2021Updated 5 years ago
- Translate the source code of Veriog version to Spinalhdl version☆10Jul 1, 2021Updated 4 years ago
- ☆11Feb 16, 2019Updated 6 years ago
- Models of finite automata (DFA, NFA) with support of common operations and easily readable creation of objects☆14Feb 4, 2019Updated 7 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆32Mar 13, 2025Updated 11 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- OmniXtend cache coherence protocol☆82Jun 10, 2025Updated 8 months ago
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 3 months ago
- Open-source high-performance non-blocking cache☆93Dec 3, 2025Updated 2 months ago
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 3 months ago
- Mako is a low-pause, high-throughput garbage collector designed for memory-disaggregated datacenters.☆15Sep 2, 2024Updated last year
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 6 years ago
- ☆15Updated this week