jiegec / fpu-wrappersLinks
Wrappers for open source FPU hardware implementations.
☆37Updated last month
Alternatives and similar repositories for fpu-wrappers
Users that are interested in fpu-wrappers are comparing it to the libraries listed below
Sorting:
- Run Rocket Chip on VCU128☆30Updated 2 months ago
- chipyard in mill :P☆77Updated 2 years ago
- ☆33Updated 9 months ago
- Open-source non-blocking L2 cache☆52Updated this week
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- A prototype GUI for chisel-development☆51Updated 5 years ago
- ☆90Updated 3 weeks ago
- The 'missing header' for Chisel☆22Updated 9 months ago
- A Heterogeneous GPU Platform for Chipyard SoC☆41Updated this week
- Synthesisable SIMT-style RISC-V GPGPU☆48Updated 6 months ago
- Chisel Cheatsheet☆34Updated 2 years ago
- Open source high performance IEEE-754 floating unit☆88Updated last year
- Intel Compiler for SystemC☆27Updated 2 years ago
- Open-source high-performance non-blocking cache☆92Updated last month
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Updated 3 weeks ago
- Chisel RISC-V Vector 1.0 Implementation☆126Updated 3 months ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆47Updated 7 months ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆33Updated last week
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21Updated 8 months ago
- A Rocket-based RISC-V superscalar in-order core☆36Updated 3 months ago
- Various examples for Chisel HDL☆30Updated 3 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Updated 7 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Floating point modules for CHISEL☆32Updated 11 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆44Updated 6 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last month
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year