jiegec / fpu-wrappersLinks
Wrappers for open source FPU hardware implementations.
☆32Updated last year
Alternatives and similar repositories for fpu-wrappers
Users that are interested in fpu-wrappers are comparing it to the libraries listed below
Sorting:
- The 'missing header' for Chisel☆20Updated 3 months ago
- Open source high performance IEEE-754 floating unit☆75Updated last year
- ☆33Updated 3 months ago
- Intel Compiler for SystemC☆23Updated 2 years ago
- Open-source non-blocking L2 cache☆43Updated this week
- ☆40Updated 2 weeks ago
- For contributions of Chisel IP to the chisel community.☆62Updated 7 months ago
- Run Rocket Chip on VCU128☆30Updated 6 months ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- ☆30Updated 6 months ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- This repo includes XiangShan's function units☆26Updated 2 weeks ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆33Updated last week
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆28Updated 5 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated last month
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated this week
- chipyard in mill :P☆78Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆18Updated last month
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆16Updated 7 months ago
- Lower chisel memories to SRAM macros☆12Updated last year
- Various examples for Chisel HDL☆29Updated 3 years ago
- ☆30Updated 2 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆33Updated last year
- A Rocket-based RISC-V superscalar in-order core☆33Updated last month