Alternatives and similar repositories for UberDDR3

Users that are interested in UberDDR3 are comparing it to the libraries listed below

• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆509Updated 3 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆367Updated this week
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆311Updated 4 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆374Updated last year
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆587Updated 5 months ago
• jamieiles / uart
  Verilog UART
  ☆180Updated 12 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆309Updated last year
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆235Updated 2 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆654Updated last week
• ultraembedded / core_jpeg
  High throughput JPEG decoder in Verilog for FPGA
  ☆241Updated 3 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆283Updated last week
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆342Updated 8 years ago
• SpinalHDL / NaxRiscv
  ☆295Updated last month
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆155Updated 2 years ago
• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆261Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆453Updated 3 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆527Updated 2 weeks ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆141Updated 6 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆641Updated 6 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆156Updated 2 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆297Updated 2 weeks ago
• alexforencich / verilog-uart
  Verilog UART
  ☆505Updated 6 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆665Updated 2 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆282Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆209Updated 6 months ago
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆256Updated 6 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆347Updated 6 months ago
• klyone / opencores-ip
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆112Updated 9 years ago
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆312Updated 6 months ago