Alternatives and similar repositories for UberDDR3

Users that are interested in UberDDR3 are comparing it to the libraries listed below

• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆533Updated 4 years ago
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆330Updated last month
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆507Updated 3 weeks ago
• jamieiles / uart
  Verilog UART
  ☆186Updated 12 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆609Updated 7 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆397Updated 2 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆318Updated last year
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆301Updated 2 months ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆235Updated 3 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆680Updated 2 weeks ago
• ultraembedded / core_jpeg
  High throughput JPEG decoder in Verilog for FPGA
  ☆247Updated 3 years ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆351Updated 8 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆159Updated 3 years ago
• klyone / opencores-ip
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆125Updated 10 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆168Updated 4 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆216Updated last year
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆162Updated 6 years ago
• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆289Updated this week
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆128Updated 3 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆515Updated 9 months ago
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆262Updated 6 years ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆302Updated last week
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆313Updated 2 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆158Updated 9 months ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆459Updated last week
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆310Updated 9 months ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆146Updated last year
• ultraembedded / FPGAmp
  720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
  ☆288Updated 5 years ago