AngeloJacobo / UberDDR3
Opensource DDR3 Controller
☆272Updated this week
Alternatives and similar repositories for UberDDR3:
Users that are interested in UberDDR3 are comparing it to the libraries listed below
- A DDR3 memory controller in Verilog for various FPGAs☆420Updated 3 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆244Updated last month
- AXI interface modules for Cocotb☆237Updated last year
- Common SystemVerilog components☆578Updated this week
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆307Updated 10 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆456Updated 2 weeks ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆264Updated 4 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆209Updated 4 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆145Updated 2 weeks ago
- A Fast, Low-Overhead On-chip Network☆178Updated this week
- Verilog digital signal processing components☆129Updated 2 years ago
- SDRAM controller with AXI4 interface☆87Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆133Updated last week
- Bus bridges and other odds and ends☆522Updated 3 weeks ago
- A full-speed device-side USB peripheral core written in Verilog.☆226Updated 2 years ago
- CORE-V Family of RISC-V Cores☆234Updated 2 weeks ago
- PCI express simulation framework for Cocotb☆152Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆307Updated 2 months ago
- ☆275Updated this week
- Fully parametrizable combinatorial parallel LFSR/CRC module☆144Updated this week
- Verilog Configurable Cache☆171Updated 3 months ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Fabric generator and CAD tools☆162Updated this week
- Verilog implementation of a RISC-V core☆108Updated 6 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆162Updated 3 months ago
- High throughput JPEG decoder in Verilog for FPGA☆221Updated 2 years ago
- A simple, basic, formally verified UART controller☆290Updated last year
- VeeR EL2 Core☆265Updated this week
- SystemVerilog to Verilog conversion☆595Updated last week
- AHB3-Lite Interconnect☆84Updated 9 months ago